Hi all,

I am using IUS82, MMSIM 711, IC 6.1.3

I am trying to simulate a co-simulation of vhdl, verilog, and spectre
in config view.
The simulation stops with this errors (attached the part of the log
file below)

Thanks a lot for your help

Cheers
Dinac

********************************************************************************
.........
........
ncvlog: Memory Usage - 9.5M program + 8.7M data = 18.2M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 90.4%
cpu)
Successfully compiled ('mixspi_vco' 'top_design' 'schematic').
Compilation successful.
ncelab(64): 08.20-s018: (c) Copyright 1995-2009 Cadence Design
Systems, Inc.
ncelab: *E,NOUNIT: Unable to find a unit named
'mixspi_vco.top_design:schematic' in the libraries.
ncelab: *E,NOUNIT: Unable to find a unit named
'mixspi_vco.cds_globals:top_design_
config_design_SPI_VCO' in the libraries.
ncelab: Memory Usage - 24.1M program + 21.4M data = 45.4M total
ncelab: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 78.3%
cpu)
Failed to elaborate ("mixspi_vco" "top_design"
"config_design_SPI_VCO").

dinac wrote, on 01/13/10 09:30:
> Hi all,
> 
> I am using IUS82, MMSIM 711, IC 6.1.3
> 
> I am trying to simulate a co-simulation of vhdl, verilog, and spectre
> in config view.
> The simulation stops with this errors (attached the part of the log
> file below)
> 
> Thanks a lot for your help
> 
> Cheers
> Dinac
> 
> ********************************************************************************
> ........
> .......
> ncvlog: Memory Usage - 9.5M program + 8.7M data = 18.2M total
> ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 90.4%
> cpu)
> Successfully compiled ('mixspi_vco' 'top_design' 'schematic').
> Compilation successful.
> ncelab(64): 08.20-s018: (c) Copyright 1995-2009 Cadence Design
> Systems, Inc.
> ncelab: *E,NOUNIT: Unable to find a unit named
> 'mixspi_vco.top_design:schematic' in the libraries.
> ncelab: *E,NOUNIT: Unable to find a unit named
> 'mixspi_vco.cds_globals:top_design_
> config_design_SPI_VCO' in the libraries.
> ncelab: Memory Usage - 24.1M program + 21.4M data = 45.4M total
> ncelab: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 78.3%
> cpu)
> Failed to elaborate ("mixspi_vco" "top_design"
> "config_design_SPI_VCO").

Too little information, I'm afraid.

Can you contact Cadence Customer Support - we can then guide you through 
providing all the right information, or maybe take a look at your setup remotely.

Regards,

Andrew.

Andrew thanks for your reply.
Made some trials, the simulation succeeds with IUS82 32bit with AMS
environment. But the simulation with ADE stops with another error
messages.
Mean while, I will try to contact the cadence support team soon

Thanks a lot

Cheers
Dinac

**************************
ncvhdl: 08.20-s018: (c) Copyright 1995-2009 Cadence Design Systems,
Inc.
.../spi_digi/spislave14/entity/vhdl.vhms:
USE	work.SPIpkg14.ALL;
   	    |
ncvhdl_p: *E,SELLIB (../spi_digi/spislave14/entity/vhdl.vhms,59|8):
unit (SPIPKG14) not found in library (SPI_DIGI).
	addr    : OUT STD_LOGIC_ADDR;	-- register address
	                           |
ncvhdl_p: *E,IDENTU (../spi_digi/spislave14/entity/vhdl.vhms,69|28):
identifier (STD_LOGIC_ADDR) is not declared [10.3].
	data_wr	: OUT STD_LOGIC_DATA;	-- data bus for writing register
	       	                   |
ncvhdl_p: *E,IDENTU (../spi_ihpdigi/spislave14/entity/vhdl.vhms,72|
28): identifier (STD_LOGIC_DATA) is not declared [10.3].
	data_rd : IN  STD_LOGIC_DATA);	-- data bus for reading register
	                           |
ncvhdl_p: *E,IDENTU (../spi_digi/spislave14/entity/vhdl.vhms,73|28):
identifier (STD_LOGIC_DATA) is not declared [10.3].
ncvhdl_p: *W,DLMKSL: Unable to build source link ../spi_digi/
spislave14/entity/vhdl.vhms (File exists).
	errors: 4, warnings: 1
ncvhdl_p: Memory Usage - 8.3M program + 5.1M data = 13.4M total
ncvhdl: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 28.0%
cpu)
Failed to compile ('spi_digi' 'spislave14' 'entity').
ncvhdl: 08.20-s018: (c) Copyright 1995-2009 Cadence Design Systems,
Inc.
...........
..........
.....................