Three questions:VCxBULK, propagation delay,and timing clock.

Hi all, Now I need some help. First I want to know a term:VCxBULK. For example, VC12BULK in STM-1. I think it is a whole payload area of STM-1which is filled with VC12. And its rate is equal to 155M. Other payloads as VC11BULK,VC3BULK,VC4BULK are the same rate as VC12BULK,155M. The difference between them is mapping structure only. What kind of testing or situation will use these payloads? You konw, in the most often testing, we use STM1/VC4BULK to test STM-1 interface. What purpose will use 1.5M,VC11BULK,2M,VC12BULK...? Next is about propagation delay.Is there any recommendation or specification about the target of propagation delay in PDH\SDH\DWDM? Last one is clock related.We often use 2MHz or 2Mbit as a timing clock.I can't understand their difference and usage. On the other hand, do those line rate(STM1,STM4,STM16,etc) operate on their own working clock? If any,why? Thanks , Ling

Hello Ling, You asked: > First I want to know a term:VCxBULK. Because I was not familiar with this term I searched and found: http://testworx.ca/E-Events/upload/Manual/SDHB.pdf It appears to be a term used only by this company. IMO it means a complete VC-x signal, i.e. overhead and payload. > For example, VC12BULK in STM-1. One of the 63 VC-12 signals in an STM-1, the testequipment allows you to select one (see page 41) > I think it is a whole payload area of STM-1which is filled with VC12. > And its rate is equal to 155M. No, the output of this testbox is STM-1 and you can select to test one VC-12 in this signal. > Other payloads as > VC11BULK,VC3BULK,VC4BULK are the same rate as VC12BULK,155M. The > difference between them is mapping structure only. Indeed. > What kind of testing or situation will use these payloads? You konw, in > the most often testing, we use STM1/VC4BULK to test STM-1 interface. > What purpose will use 1.5M,VC11BULK,2M,VC12BULK...? You may want to test lower order crossconnects, or lower order tributaries, e.g. an E1 interface. > Next is about propagation delay.Is there any recommendation or > specification about the target of propagation delay in PDH\SDH\DWDM? There is not much you can do about the propagation delay on the fiber (~5 ms per 1000 km) it is a design objective for equipment to minimise the transfer delay from input to output (less than 50 microseconds is good). > Last one is clock related.We often use 2MHz or 2Mbit as a timing > clock.I can't understand their difference and usage. On the other hand, > do those line rate(STM1,STM4,STM16,etc) operate on their own working > clock? If any,why? The 2 MHz sinusoidal or 2 Mbit/s E1 signals are used as reference clocks to start a timing hierarchy. Lower in the hierarchy the STM-N clock recovered from the node higher in the timing hierarchy can will be used as timing reference, and as output clock to nodes lower in the timing hierarchy. Cheers, Huub. -- reply to hhelvooort with 2 'o's ================================================================ http://members.chello.nl/hhelvoort/ ================================================================ Always remember that you are unique...just like everyone else...

Ni hao Liu, You wrote: > Thank you! :-) OK, glad to help you. > BTW, I sent you email to your @chello.nl a few days ago. But I get no > respond. Yes, I received that email when I was on a trip to Japan for an SDH experts standards meeting. And by sending the answer to the list I may also help others ;-) Cheers, Huub. -- reply to hhelvooort with 2 'o's ================================================================ http://members.chello.nl/hhelvoort/ ================================================================ Always remember that you are unique...just like everyone else...

Huub van Helvoort wrote: > You asked: > > > First I want to know a term:VCxBULK. > > Because I was not familiar with this term I searched and found: > http://testworx.ca/E-Events/upload/Manual/SDHB.pdf > > It appears to be a term used only by this company. > IMO it means a complete VC-x signal, i.e. overhead and payload. The term is actually used by several test equipment vendors. They use it to name a VC-x of which the C-x payload is completely filled with a "bulk" test signal, e.g. PRBS, i.e. without any mapping. This test signal is opposed to a substructured VC-x or a C-x with PDH mapping (or other client mapping). It allows one to test all SDH functionality except the mapping of tributary signals. Regards, Bert

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