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Filter Design, group delay

Hello,

I am looking for a way to obtain the lowest group delay.
The specifications are;

Lowpass filter
fpass=1kHz with 3dB Ripple
fstop=4kHz 
Attenuation 60dB (between 4kHz and 20kHz or between 4kHz and 97.5kHz)
with sampling frequency: 195kHz
up to 1kHz linear phase and constant group delay (needed)

If I use Generalized Equiripple FIR filter of Matlab fda toolbox, th
minimum order is 115 (so 57.5 Tabs delay)

Is it possible to obtain a new filter which has a delay less than 57.
Tabs for the given specifications?

Best Regards

Gokhan


0
apadin78 (2)
10/12/2007 2:58:22 AM
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On 12 Okt, 04:58, "gapaydin" <apadi...@yahoo.com> wrote:
> Hello,
>
> I am looking for a way to obtain the lowest group delay.
> The specifications are;
>
> Lowpass filter
> fpass=1kHz with 3dB Ripple
> fstop=4kHz
> Attenuation 60dB (between 4kHz and 20kHz or between 4kHz and 97.5kHz)
> with sampling frequency: 195kHz
> up to 1kHz linear phase and constant group delay (needed)
>
> If I use Generalized Equiripple FIR filter of Matlab fda toolbox, the
> minimum order is 115 (so 57.5 Tabs delay)
>
> Is it possible to obtain a new filter which has a delay less than 57.5
> Tabs for the given specifications?

I would be very surprised if you can reduce the group
delay significantly. Since you require constant group
delay you are commited to symmetric FIR filters.
Which means that the task is to design the shortest
symmetric FIR filter which attains the spec.

You may be able to save a couple of coefficients relative
to the one you already have, but not very many, and it
will almost certainly not be worth the extra effort.

Rune

0
allnor (8509)
10/12/2007 10:31:29 AM
On 12 Okt., 04:58, "gapaydin" <apadi...@yahoo.com> wrote:
> Hello,
>
> I am looking for a way to obtain the lowest group delay.
> The specifications are;
>
> Lowpass filter
> fpass=1kHz with 3dB Ripple
> fstop=4kHz
> Attenuation 60dB (between 4kHz and 20kHz or between 4kHz and 97.5kHz)
> with sampling frequency: 195kHz
> up to 1kHz linear phase and constant group delay (needed)

What's the allowable ripple on the group delay?

0
andor.bariska (1307)
10/12/2007 11:32:20 AM
On Oct 12, 7:32 am, Andor <andor.bari...@gmail.com> wrote:
> On 12 Okt., 04:58, "gapaydin" <apadi...@yahoo.com> wrote:
>
> > Hello,
>
> > I am looking for a way to obtain the lowest group delay.
> > The specifications are;
>
> > Lowpass filter
> > fpass=1kHz with 3dB Ripple
> > fstop=4kHz
> > Attenuation 60dB (between 4kHz and 20kHz or between 4kHz and 97.5kHz)
> > with sampling frequency: 195kHz
> > up to 1kHz linear phase and constant group delay (needed)
>
> What's the allowable ripple on the group delay?

good point...

Or to ask the question to the OP a diffeent way...

OP, are you concerned about minimizing GROUP DELAY...or   GROUP DELAY
___VARIATION__.

I notice many times people will use the term "Group Delay"  when they
mean "Group Delay variation"   or "Group Delay ripple".   Group Delay
itself is usally not a problem, but group delay ripple can be.  FIR
filters have no group delay ripple but they do have group delay.

Which are you concerned about and why?



Mark

0
makolber (619)
10/12/2007 1:32:03 PM
"Mark" <makolber@yahoo.com> wrote in message 
news:1192195923.763770.301250@i13g2000prf.googlegroups.com...
>>
>> What's the allowable ripple on the group delay?
>
> good point...
>
> Or to ask the question to the OP a diffeent way...
>
> OP, are you concerned about minimizing GROUP DELAY...or   GROUP DELAY
> ___VARIATION__.
>
> I notice many times people will use the term "Group Delay"  when they
> mean "Group Delay variation"   or "Group Delay ripple".   Group Delay
> itself is usally not a problem, but group delay ripple can be.  FIR
> filters have no group delay ripple but they do have group delay.
>
> Which are you concerned about and why?
>

Great question Mark! 


0
fmarshallx1 (1639)
10/12/2007 3:30:51 PM
>On 12 Okt., 04:58, "gapaydin" <apadi...@yahoo.com> wrote:
>> Hello,
>>
>> I am looking for a way to obtain the lowest group delay.
>> The specifications are;
>>
>> Lowpass filter
>> fpass=1kHz with 3dB Ripple
>> fstop=4kHz
>> Attenuation 60dB (between 4kHz and 20kHz or between 4kHz and 97.5kHz)
>> with sampling frequency: 195kHz
>> up to 1kHz linear phase and constant group delay (needed)
>
>What's the allowable ripple on the group delay?
>
>
Sorry for my late reply, considering Finite Impulse Response
the group delay ripple is zero. 

However; if Infinite Impulse Response is used, the group delay with th
smallest ripple (because of audio application) up to passband frequenc
can be considered. I tried this but I have not found better group dela
(smaller than 57.5 Taps). I want to use this filter for real time audi
application. So, the minimum ripple on group delay can be considere
maybe...

Best Regards and thank you for your mails...
0
apadin78 (2)
10/14/2007 12:12:58 PM
Hint, the 3 dB passband ripple may give some indication on the maximu
error you're willing to tolerate. 
If I consider amplitude and phase of a sine wave a vector, a 3 dB gives a
error vector (difference between ideal and actual) that is 0.707 times th
magnitude of the input vector.
Now if I consider that my error budget, and reduce the 3 dB amplitud
ripple to for example 1 dB, it gives me a lot of error vector magnitude t
put on the phase error.
Note, in some cases the argumentation makes sense. But in other cases (fo
example phase modulation) it doesn't work.

Then, if it's about audio, the ear is quite insensitive to phase.

-mn
0
mnentwig (306)
10/14/2007 4:51:25 PM
"gapaydin" <apadin78@yahoo.com> wrote in message 
news:rbednVSS7dZXmo_anZ2dnUVZ_judnZ2d@giganews.com...
> >On 12 Okt., 04:58, "gapaydin" <apadi...@yahoo.com> wrote:
>>> Hello,
>>>
>>> I am looking for a way to obtain the lowest group delay.
>>> The specifications are;
>>>
>>> Lowpass filter
>>> fpass=1kHz with 3dB Ripple
>>> fstop=4kHz
>>> Attenuation 60dB (between 4kHz and 20kHz or between 4kHz and 97.5kHz)
>>> with sampling frequency: 195kHz
>>> up to 1kHz linear phase and constant group delay (needed)
>>
>>What's the allowable ripple on the group delay?
>>
>>
> Sorry for my late reply, considering Finite Impulse Response
> the group delay ripple is zero.
>
> However; if Infinite Impulse Response is used, the group delay with the
> smallest ripple (because of audio application) up to passband frequency
> can be considered. I tried this but I have not found better group delay
> (smaller than 57.5 Taps). I want to use this filter for real time audio
> application. So, the minimum ripple on group delay can be considered
> maybe...

Careful ... only symmetrical FIR filter group delay ripple is zero.
In fact, you may want to have a nonsymmetrical FIR filter to get reduced 
delay if that's really what you want.

Consider these rules of thumb:

The narrowest transition in the filter response (i.e. from passband to 
stopband or stopband to passband) determines the length of the filter.  The 
length is proportional to the reciprocal of the narrowest transition width. 
So, to have a shorter filter, increase the frequency span of the 
transitions.  In your case this "rule" would use the 3kHz transition width 
to get a time span of 0.333msec.  At your sample rate of 195kHz, this would 
be 65 taps - not so far off from 57.  At these lengths change with number of 
taps is quite gradual.

Getting linear phase with a FIR filter roughly increases the length of the 
filter by a factor of 2.  So, consider non linear phase FIR filters.  Or 
consider an IIR filter.

Schussler developed a method for designing non linear phase FIR filters.  If 
I remember it correctly, it goes like this:

1) Design a linear phase / symmetrical odd-length FIR filter using minimax 
criterion - as with Parks-McClellan's program.  Require that all of the stop 
bands have the same ripple (just use the same weight).  Because the filter 
is symmetrical / even in time / the frequency response will be purely real. 
Later, the stopband ripple will increase by a factor of 2 in dB so you may 
want to make sure at this step that the stopband ripple is low enough to 
accomodate this.  If you need 30dB, design for 60dB.

2) "Lift" the filter response by a constant that's equal to the value of the 
stop band ripple peaks.  This makes the negative-valued peaks become double 
zeros.  Adding a constant to the frequency response changes the middle 
coefficient of the unit sample response and the new filter has a new 
polynomial in z^-1.

3) Factor the polynomial.  There will be a constellation of quads of roots 
that are reciprocal/symmetric and symmetrical about fs/2 on radii of the 
unit circle in the z plane.   Remove one symmetrical pair of each of these - 
leaving single zeros in place of double zeros in the stop band and reducing 
the order of the polynomial by 2.  In essence, find one of the (many) square 
roots of the filter response.

Note: As above, this step has quite a few choices of which roots to remove. 
If you remove all the indicated roots outside the unit circle then the 
resulting filter tends to minimum phase (which is what you want for minimum 
delay).  If you remove all the indicated roots inside the unit circle then 
the resulting filter tends to maximum phase (the opposite).

Either way, the result is a non linear phase / unsymmetrical FIR filter 
whose response is the square root of the original.  So, passbands with value 
1.0 will remain at 1.0.  Passband ripple of 1.1 and .9 will become 1.05 and 
..95 - making the passband amplitude ripple less.  Stopband ripple of 10^-6 
will become 10^-3 - making the stopband ripple worse.

Don't expect huge improvements.  Maybe the improvement you get will be worth 
the effort.
And, none of this addresses your phase requirement - but it may be a 
starting point.  It makes me wonder what happens if you retain the quad 
roots in the passband - something like that....  I'd think they would 
dominate the phase response there.

You might also consider the Meteor program which, with some effort, I 
believe can accomodate phase criteria.  There may be newer, better such 
programs.

Hmmm.... I just tried applying the Parks-McClellan and the result show, not 
surprisingly, that *all* of the degrees of freedom go into the stop band. 
That's because the passband is so narrow - there are no "ripples" at all 
except the deviation right at the edge of the passband.  And, the length of 
the symmetric filter has to be more like 117 or so to get the stopband 
attenuation.  That makes me wonder how you got 57?

Fred 


0
fmarshallx1 (1639)
10/15/2007 5:31:51 AM
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I've pulled a DSP Group Teak Lite DSP development board out of the bin at work. It's about 3-4 years old. Their web site asks you to login before you can look at docs an support S/W etc. Does anyone have an old support login for this site? Cheers, Alfie. ...

US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45328832401)
US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45328832401) ======================================================================================== Position: VLSI Circuit Designer Reference: SMC01756 Location: Austin TX Duration: DH Skills: BSEE (MSEE preferred). 5+yrs exp in CMOS custom circuit design. Microprocessor or DSP design experience. Core skills must include high performance custom circuit design and should include experience in one or more of the fo...

US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45339432408)
US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45339432408) ======================================================================================== Position: VLSI Circuit Designer Reference: SMC01756 Location: Austin TX Duration: DH Skills: BSEE (MSEE preferred). 5+yrs exp in CMOS custom circuit design. Microprocessor or DSP design experience. Core skills must include high performance custom circuit design and should include experience in one or more of the following: caches, register files, arithmetic circuits, datapath elements and timing model development. Scope: Responsible for custom circuit design, which includes schematic capture, circuit simulation, timing model creation and layout oversight. Our Client: Our client designs high performance, low-cost x86 compatible microprocessors. They have the fastest design cycle in the industry, with new designs going from concept to completion in about 9 months, 1/3 the time of the competitors. In nine years, they have shipped ten different designs with millions of units sold. Please send your current resume in confidence to <staffing@eurosoft-inc.com> ..45339432408. ...

US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45350432404)
US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45350432404) ======================================================================================== Position: VLSI Circuit Designer Reference: SMC01756 Location: Austin TX Duration: DH Skills: BSEE (MSEE preferred). 5+yrs exp in CMOS custom circuit design. Microprocessor or DSP design experience. Core skills must include high performance custom circuit design and should include experience in one or more of the fo...

US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45339432408)
US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45339432408) ======================================================================================== Position: VLSI Circuit Designer Reference: SMC01756 Location: Austin TX Duration: DH Skills: BSEE (MSEE preferred). 5+yrs exp in CMOS custom circuit design. Microprocessor or DSP design experience. Core skills must include high performance custom circuit design and should include experience in one or more of the following: caches, register files, arithmetic circuits, datapath elements and timing model development. Scope: Responsible for custom circuit design, which includes schematic capture, circuit simulation, timing model creation and layout oversight. Our Client: Our client designs high performance, low-cost x86 compatible microprocessors. They have the fastest design cycle in the industry, with new designs going from concept to completion in about 9 months, 1/3 the time of the competitors. In nine years, they have shipped ten different designs with millions of units sold. Please send your current resume in confidence to <staffing@eurosoft-inc.com> ..45339432408. ...

US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45329714407)
US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45329714407) ======================================================================================== Position: VLSI Circuit Designer Reference: SMC01756 Location: Austin TX Duration: DH Skills: BSEE (MSEE preferred). 5+yrs exp in CMOS custom circuit design. Microprocessor or DSP design experience. Core skills must include high performance custom circuit design and should include experience in one or more of the following: caches, register files, arithmetic circuits, datapath elements and timing model development. Scope: Responsible for custom circuit design, which includes schematic capture, circuit simulation, timing model creation and layout oversight. Our Client: Our client designs high performance, low-cost x86 compatible microprocessors. They have the fastest design cycle in the industry, with new designs going from concept to completion in about 9 months, 1/3 the time of the competitors. In nine years, they have shipped ten different designs with millions of units sold. Please send your current resume in confidence to <staffing@eurosoft-inc.com> ..45329714407. ...

US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45350414401)
US-TX-Austin: VLSI Circuit Designer, 5+yrs exp CMOS design, DSP design; DH (45350414401) ======================================================================================== Position: VLSI Circuit Designer Reference: SMC01756 Location: Austin TX Duration: DH Skills: BSEE (MSEE preferred). 5+yrs exp in CMOS custom circuit design. Microprocessor or DSP design experience. Core skills must include high performance custom circuit design and should include experience in one or more of the fo...

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Resources last updated: 3/29/2016 11:55:43 PM