Fixed point implementation of 4'th order IIR filters

Hi

Does anyone have some guidelines on how to implement a 4'th order low-pass
Butterworth IIR filter in fixed point. My cut-off frequency is relatively
close to the DC frequency so high precision is needed for the coefficients.
What about realization structure and so on!

I have implemented the bit-flipping algorithm in
http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization of
coefficients
and it indeed works, but does some other techniques allow for further
reductions of number of bits used to represent the coefficients.

Thomas


0
Heureka
11/5/2003 11:43:23 PM
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I've found the normalized lattice-ladder approach yields low distortion even
at low frequencies.  The cost is more multiplies per filter.

Is this a hardware/FPGA implementation?

"Heureka" <stoltzo@hotmail.com> wrote in message
news:boc1up$l86$1@news.cybercity.dk...
> Hi
>
> Does anyone have some guidelines on how to implement a 4'th order low-pass
> Butterworth IIR filter in fixed point. My cut-off frequency is relatively
> close to the DC frequency so high precision is needed for the
coefficients.
> What about realization structure and so on!
>
> I have implemented the bit-flipping algorithm in
> http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization of
> coefficients
> and it indeed works, but does some other techniques allow for further
> reductions of number of bits used to represent the coefficients.
>
> Thomas
>
>


0
Jon
11/6/2003 12:13:00 AM
Might have to go with 32 bit filter states and/or coefficients.  Or
you can try some of the noise shaping that's been described in here
every now and then.  

I would cascade 2, 2nd order biquads ( if it's being done in software
).

Robert

www.gldsp.com

"Heureka" <stoltzo@hotmail.com> wrote:

>Hi
>
>Does anyone have some guidelines on how to implement a 4'th order low-pass
>Butterworth IIR filter in fixed point. My cut-off frequency is relatively
>close to the DC frequency so high precision is needed for the coefficients.
>What about realization structure and so on!
>
>I have implemented the bit-flipping algorithm in
>http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization of
>coefficients
>and it indeed works, but does some other techniques allow for further
>reductions of number of bits used to represent the coefficients.
>
>Thomas
>


( modify address for return email )

www.numbersusa.com
www.americanpatrol.com
0
r_obert
11/6/2003 4:31:00 AM
Heureka wrote:

> Hi
> 
> Does anyone have some guidelines on how to implement a 4'th order
> low-pass Butterworth IIR filter in fixed point. My cut-off
> frequency is relatively close to the DC frequency so high
> precision is needed for the coefficients. What about realization
> structure and so on!
> 
> I have implemented the bit-flipping algorithm in
> http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization
> of coefficients
> and it indeed works, but does some other techniques allow for
> further reductions of number of bits used to represent the
> coefficients.
> 
> Thomas

Which is your relative cut-off frequency  Fc/Fs?
How many real bits has your signal?
How many bits do you need after the filter stage?

Bernhard

0
Bernhard
11/6/2003 7:01:21 AM
Hello:

Basic Guidelines:  Use 2 2nd order Direct Form I (two delay lines, to avoid
overflow of internal filter states) cascaded sections.  You most likely will
need to halve the a1 coeficient in each stage (if it is greater than 1) and
do two macs on that part of the calculation.  For low fc/fs, you may need 32
bit recursive data paths.

Matlab has tools to take general transfer functions B(z)/A(z) and
restructure them to cascaded second order sections.

Regards
-S
www.appliedsignalprocessing.com

"Heureka" <stoltzo@hotmail.com> wrote in message
news:boc1up$l86$1@news.cybercity.dk...
> Hi
>
> Does anyone have some guidelines on how to implement a 4'th order low-pass
> Butterworth IIR filter in fixed point. My cut-off frequency is relatively
> close to the DC frequency so high precision is needed for the
coefficients.
> What about realization structure and so on!
>
> I have implemented the bit-flipping algorithm in
> http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization of
> coefficients
> and it indeed works, but does some other techniques allow for further
> reductions of number of bits used to represent the coefficients.
>
> Thomas
>
>


0
Shawn
11/6/2003 5:16:51 PM
Sorry for my late reply!

The filters are to be implemented on a FPGA. The cutoff frequency is fs/64.
When I convert the floating point coefficients
linearly I have to use 30 bit in order to have a stop band attenuation at 70
dB. With the bit.flipiing algorithm I can get the bit number down to 20 bit.
I need to use as few multiplications as possible, since power consumption is
of the essence - but area is too.

Can anyone recommend some nice litterature adressing this issue!

Thomas


"Bernhard Holzmayer" <holzmayer.bernhard@deadspam.com> wrote in message
news:1097769.KRe6XMYa8L@holzmayer.ifr.rt...
> Heureka wrote:
>
> > Hi
> >
> > Does anyone have some guidelines on how to implement a 4'th order
> > low-pass Butterworth IIR filter in fixed point. My cut-off
> > frequency is relatively close to the DC frequency so high
> > precision is needed for the coefficients. What about realization
> > structure and so on!
> >
> > I have implemented the bit-flipping algorithm in
> > http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization
> > of coefficients
> > and it indeed works, but does some other techniques allow for
> > further reductions of number of bits used to represent the
> > coefficients.
> >
> > Thomas
>
> Which is your relative cut-off frequency  Fc/Fs?
> How many real bits has your signal?
> How many bits do you need after the filter stage?
>
> Bernhard
>


0
Heureka
11/6/2003 7:38:37 PM
FPGA with minimal multiplies?  In that case, scratch my previous idea of the
normalized Lattice-Ladder implementation.

"Heureka" <stoltzo@hotmail.com> wrote in message
news:3faaa32c$0$69926$edfadb0f@dread12.news.tele.dk...
> Sorry for my late reply!
>
> The filters are to be implemented on a FPGA. The cutoff frequency is
fs/64.
> When I convert the floating point coefficients
> linearly I have to use 30 bit in order to have a stop band attenuation at
70
> dB. With the bit.flipiing algorithm I can get the bit number down to 20
bit.
> I need to use as few multiplications as possible, since power consumption
is
> of the essence - but area is too.
>
> Can anyone recommend some nice litterature adressing this issue!
>
> Thomas
>
>
> "Bernhard Holzmayer" <holzmayer.bernhard@deadspam.com> wrote in message
> news:1097769.KRe6XMYa8L@holzmayer.ifr.rt...
> > Heureka wrote:
> >
> > > Hi
> > >
> > > Does anyone have some guidelines on how to implement a 4'th order
> > > low-pass Butterworth IIR filter in fixed point. My cut-off
> > > frequency is relatively close to the DC frequency so high
> > > precision is needed for the coefficients. What about realization
> > > structure and so on!
> > >
> > > I have implemented the bit-flipping algorithm in
> > > http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization
> > > of coefficients
> > > and it indeed works, but does some other techniques allow for
> > > further reductions of number of bits used to represent the
> > > coefficients.
> > >
> > > Thomas
> >
> > Which is your relative cut-off frequency  Fc/Fs?
> > How many real bits has your signal?
> > How many bits do you need after the filter stage?
> >
> > Bernhard
> >
>
>


0
Jon
11/7/2003 1:47:17 AM
Hi Thomas!

You can also use Lattice Digital Wave filter sections to implement 1-st 
and 2-nd order allpass sections in cascade. From these allpass sections 
in cascade one can form a sum or difference dependent on how the filter 
should act (LP, HP etc.). The resulting filter require minimal number of 
  multipliers and wordlength.

Jon Harris wrote:
> FPGA with minimal multiplies?  In that case, scratch my previous idea of the
> normalized Lattice-Ladder implementation.
> 
> "Heureka" <stoltzo@hotmail.com> wrote in message
> news:3faaa32c$0$69926$edfadb0f@dread12.news.tele.dk...
> 
>>Sorry for my late reply!
>>
>>The filters are to be implemented on a FPGA. The cutoff frequency is
> 
> fs/64.
> 
>>When I convert the floating point coefficients
>>linearly I have to use 30 bit in order to have a stop band attenuation at
> 
> 70
> 
>>dB. With the bit.flipiing algorithm I can get the bit number down to 20
> 
> bit.
> 
>>I need to use as few multiplications as possible, since power consumption
> 
> is
> 
>>of the essence - but area is too.
>>
>>Can anyone recommend some nice litterature adressing this issue!
>>
>>Thomas
>>
>>
>>"Bernhard Holzmayer" <holzmayer.bernhard@deadspam.com> wrote in message
>>news:1097769.KRe6XMYa8L@holzmayer.ifr.rt...
>>
>>>Heureka wrote:
>>>
>>>
>>>>Hi
>>>>
>>>>Does anyone have some guidelines on how to implement a 4'th order
>>>>low-pass Butterworth IIR filter in fixed point. My cut-off
>>>>frequency is relatively close to the DC frequency so high
>>>>precision is needed for the coefficients. What about realization
>>>>structure and so on!
>>>>
>>>>I have implemented the bit-flipping algorithm in
>>>>http://www.cmsa.wmin.ac.uk/~artur/pdf/Paper16.pdf for quantization
>>>>of coefficients
>>>>and it indeed works, but does some other techniques allow for
>>>>further reductions of number of bits used to represent the
>>>>coefficients.
>>>>
>>>>Thomas
>>>
>>>Which is your relative cut-off frequency  Fc/Fs?
>>>How many real bits has your signal?
>>>How many bits do you need after the filter stage?
>>>
>>>Bernhard
>>>
>>
>>
> 
> 

0
Michael
11/7/2003 8:48:00 AM
Reply:
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