f



Negative Group Delay Circuit

http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf

They appear to get an output before there is an input! Surely some
mistake...



Hardy
0
gyansorova (941)
7/9/2011 1:30:37 AM
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HardySpicer wrote:
> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
> They appear to get an output before there is an input! Surely some
> mistake...


Unfortunately they found it had already been reported in last month's 
journal. ;)

I once wasted an entire day trying to do that (back when I was 21 or 
so).  These guys don't seem to have got the memo about causality.

Love to see them build one that works.

Cheers

Phil Hobbs


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
0
7/9/2011 1:34:26 AM
On Jul 8, 9:30=A0pm, HardySpicer <gyansor...@gmail.com> wrote:
> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
> They appear to get an output before there is an input! Surely some
> mistake...

No mistake. They really do appear to advance the signal. They don't
actually advance it, but they do appear to.

Jerry
--
Engineering is the art of making what you want from things you can
get.
0
jya (12871)
7/9/2011 1:35:14 AM
> HardySpicer wrote:
>> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>>
>> They appear to get an output before there is an input! Surely some
>> mistake...
>>

The real input is when the switch is closed.

As the article itself points out, neither signal is actually delayed at 
all. Both appear as soon as the switch is closed.

The apparent advancement of the output pulse arises because the observer 
is attaching an inappropriate significance to its shape.

Now, you might think you could put a switch after the signal labelled 
input, and thereby achieve a reverse causality. But it wouldn't work as 
you expect. You'd see a discontinuity in the output signal that occurs 
at the time you open the switch, but not before.

Sylvia.
0
sylvia (13)
7/9/2011 2:18:31 AM
"HardySpicer" <gyansorova@gmail.com> wrote in message 
news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
| http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
|
| They appear to get an output before there is an input! Surely some
| mistake...
|
|
|
| Hardy

OMG! Current leads voltage in a capacitor!  Who'd a thunk it?
Fig 7 shows a square wave input, but fig 8 is not square and
therefore not the input as claimed. Fig. 6 has two resistors both
labelled R1 and two capacitors both labelled C1, those guys
must have had too much saki.


0
7/9/2011 2:22:18 AM
On Fri, 08 Jul 2011 20:45:35 -0700, Les Cargill
<lcargill99@comcast.com> wrote:

>HardySpicer wrote:
>> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>>
>> They appear to get an output before there is an input! Surely some
>> mistake...


   I've read about something very similar, and it's not good:

http://www.concatenation.org/futures/whatsexpected.pdf

>>
>>
>>
>> Hardy
>
>Things are causal
>This I know
>'Cause the Second tells me so...

   Why didn't I learn THAT one at age 5 in Sunday School?

0
7/9/2011 2:50:00 AM
On Jul 8, 10:50=A0pm, Ben Bradley <ben_u_brad...@etcmail.com> wrote:
> On Fri, 08 Jul 2011 20:45:35 -0700, Les Cargill
>
....
> >Things are causal
> >This I know
> >'Cause the Second tells me so...
>
> =A0 =A0Why didn't I learn THAT one at age 5 in Sunday School?

:-)
0
rbj (4086)
7/9/2011 3:01:17 AM
On Fri, 08 Jul 2011 21:34:26 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>HardySpicer wrote:
>> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>>
>> They appear to get an output before there is an input! Surely some
>> mistake...
>
>
>Unfortunately they found it had already been reported in last month's 
>journal. ;)
>
>I once wasted an entire day trying to do that (back when I was 21 or 
>so).  These guys don't seem to have got the memo about causality.
>
>Love to see them build one that works.
>
>Cheers
>
>Phil Hobbs


http://www.edn.com/article/517407-Anticipator_circuit_speeds_signal_settling_to_a_final_value.php


John

0
jjlarkin (641)
7/9/2011 3:10:32 AM
On Jul 8, 10:50=A0pm, Ben Bradley <ben_u_brad...@etcmail.com> wrote:
> On Fri, 08 Jul 2011 20:45:35 -0700, Les Cargill
>
> <lcargil...@comcast.com> wrote:
> >HardySpicer wrote:
> >>http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
> >> They appear to get an output before there is an input! Surely some
> >> mistake...
>
> =A0 =A0I've read about something very similar, and it's not good:
>
> http://www.concatenation.org/futures/whatsexpected.pdf

That's old hat. All it takes is a dollop of thiotimoline.
(Google The Endochronic Properties of Thiotimoline et seq.)

  ...
> =A0 =A0Why didn't I learn THAT one at age 5 in Sunday School?

Unless you're older than I guess, it was old hat then too.

Jerry
--
Engineering is the art of making what you want from things you can get.
0
jya (12871)
7/9/2011 3:13:36 AM
John Larkin wrote:
> On Fri, 08 Jul 2011 21:34:26 -0400, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net>  wrote:
>
>> HardySpicer wrote:
>>> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>>>
>>> They appear to get an output before there is an input! Surely some
>>> mistake...
>>
>>
>> Unfortunately they found it had already been reported in last month's
>> journal. ;)
>>
>> I once wasted an entire day trying to do that (back when I was 21 or
>> so).  These guys don't seem to have got the memo about causality.
>>
>> Love to see them build one that works.
>>
>> Cheers
>>
>> Phil Hobbs
>
>
> http://www.edn.com/article/517407-Anticipator_circuit_speeds_signal_settling_to_a_final_value.php
>
>
> John
>

Okay, four months ago.  Must be a better time machine than I thought. ;)
(That's the one we ripped up here a few weeks ago, I remember--or is it 
just deja vu?  Time machines are so confusing.)

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
0
7/9/2011 3:33:21 AM
HardySpicer wrote:
> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
> They appear to get an output before there is an input! Surely some
> mistake...
>
>
>
> Hardy

Things are causal
This I know
'Cause the Second tells me so...

--
Les Cargill1
0
lcargill991 (563)
7/9/2011 3:45:35 AM
On Jul 9, 2:22=A0pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
wrote:
> "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
> |http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> |
> | They appear to get an output before there is an input! Surely some
> | mistake...
> |
> |
> |
> | Hardy
>
> OMG! Current leads voltage in a capacitor! =A0Who'd a thunk it?
> Fig 7 shows a square wave input, but fig 8 is not square and
> therefore not the input as claimed. Fig. 6 has two resistors both
> labelled R1 and two capacitors both labelled C1, those guys
> must have had too much saki.

I thought a lot about this, and I don't think this is just phase-
advance, but common sense tells you it must be.
What is not clear is the 2 LEDs in teh circuit, is the second one
supposed to light before the first?

Hardy
0
gyansorova (941)
7/9/2011 3:46:13 AM
On Jul 9, 1:30=A0pm, HardySpicer <gyansor...@gmail.com> wrote:
> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
> They appear to get an output before there is an input! Surely some
> mistake...
>
> Hardy

: IEEE Journal of Selected Topics in Quantum Electronics - IEEE J SEL
TOP QUANTUM ELECTR , vol. 9, no. 1, pp. 43-51, 2003
0
gyansorova (941)
7/9/2011 4:05:11 AM
"HardySpicer" <gyansorova@gmail.com> wrote in message
news:19f8dc7e-7cc4-485b-aaa0-aa89369e9de1@h8g2000yqj.googlegroups.com...
On Jul 9, 2:22 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
wrote:
> "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
> | http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf

> |
> | They appear to get an output before there is an input! Surely some
> | mistake...
> |
> |
> |
> | Hardy
>
> OMG! Current leads voltage in a capacitor! Who'd a thunk it?
> Fig 7 shows a square wave input, but fig 8 is not square and
> therefore not the input as claimed. Fig. 6 has two resistors both
> labelled R1 and two capacitors both labelled C1, those guys
> must have had too much saki.

I thought a lot about this, and I don't think this is just phase-
advance, but common sense tells you it must be.
What is not clear is the 2 LEDs in teh circuit, is the second one
supposed to light before the first?

Hardy

===========================================
Sure, no reason it shouldn't.
step 1: circuit is steady state.
step 2: delta V appears across the non-inverting input and inverting input.
step 3: through amplification the output LED lights.
step 4: through the feedback capacitor the "input" LED lights.
step 5: circuit reverts to steady state as there is no DC in the feedback
to the non-inverting input but there is to the inverting input, R3.
step 6: the output LED extinguishes.
step 7: the "input" LED extinguishes.

The "input" LED actually gets its power from the arse end of the op-amp,
not from any input source. Fig 7 doesn't show that.

This is just some students scratching out a term paper, obviously anyone can 
duplicate their results. I'd deduct marks for incorrect labelling of R1/C1.

As others have said, no effect without cause.


0
7/9/2011 7:37:41 AM
On Jul 9, 7:37=A0pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
wrote:
> "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> news:19f8dc7e-7cc4-485b-aaa0-aa89369e9de1@h8g2000yqj.googlegroups.com...
> On Jul 9, 2:22 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
> wrote:
>
>
>
> > "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> >news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com..=
..
> > |http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> > |
> > | They appear to get an output before there is an input! Surely some
> > | mistake...
> > |
> > |
> > |
> > | Hardy
>
> > OMG! Current leads voltage in a capacitor! Who'd a thunk it?
> > Fig 7 shows a square wave input, but fig 8 is not square and
> > therefore not the input as claimed. Fig. 6 has two resistors both
> > labelled R1 and two capacitors both labelled C1, those guys
> > must have had too much saki.
>
> I thought a lot about this, and I don't think this is just phase-
> advance, but common sense tells you it must be.
> What is not clear is the 2 LEDs in teh circuit, is the second one
> supposed to light before the first?
>
> Hardy
>
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> Sure, no reason it shouldn't.
> step 1: circuit is steady state.
> step 2: delta V appears across the non-inverting input and inverting inpu=
t.
> step 3: through amplification the output LED lights.
> step 4: through the feedback capacitor the "input" LED lights.
> step 5: circuit reverts to steady state as there is no DC in the feedback
> to the non-inverting input but there is to the inverting input, R3.
> step 6: the output LED extinguishes.
> step 7: the "input" LED extinguishes.
>
> The "input" LED actually gets its power from the arse end of the op-amp,
> not from any input source. Fig 7 doesn't show that.
>
> This is just some students scratching out a term paper, obviously anyone =
can
> duplicate their results. I'd deduct marks for incorrect labelling of R1/C=
1.
>
> As others have said, no effect without cause.

actually it's an IEEE trans paper. I am willing to bet you have never
even written a paper let along had a full one in IEEE.

Hardy
0
gyansorova (941)
7/9/2011 8:07:12 AM
"HardySpicer" <gyansorova@gmail.com> wrote in message 
news:b70a5b34-3783-46c1-b19b-02191f337b77@t7g2000vbv.googlegroups.com...
On Jul 9, 7:37 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
wrote:
> "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> news:19f8dc7e-7cc4-485b-aaa0-aa89369e9de1@h8g2000yqj.googlegroups.com...
> On Jul 9, 2:22 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
> wrote:
>
>
>
> > "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> >news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
> > |http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> > |
> > | They appear to get an output before there is an input! Surely some
> > | mistake...
> > |
> > |
> > |
> > | Hardy
>
> > OMG! Current leads voltage in a capacitor! Who'd a thunk it?
> > Fig 7 shows a square wave input, but fig 8 is not square and
> > therefore not the input as claimed. Fig. 6 has two resistors both
> > labelled R1 and two capacitors both labelled C1, those guys
> > must have had too much saki.
>
> I thought a lot about this, and I don't think this is just phase-
> advance, but common sense tells you it must be.
> What is not clear is the 2 LEDs in teh circuit, is the second one
> supposed to light before the first?
>
> Hardy
>
> ===========================================
> Sure, no reason it shouldn't.
> step 1: circuit is steady state.
> step 2: delta V appears across the non-inverting input and inverting 
> input.
> step 3: through amplification the output LED lights.
> step 4: through the feedback capacitor the "input" LED lights.
> step 5: circuit reverts to steady state as there is no DC in the feedback
> to the non-inverting input but there is to the inverting input, R3.
> step 6: the output LED extinguishes.
> step 7: the "input" LED extinguishes.
>
> The "input" LED actually gets its power from the arse end of the op-amp,
> not from any input source. Fig 7 doesn't show that.
>
> This is just some students scratching out a term paper, obviously anyone 
> can
> duplicate their results. I'd deduct marks for incorrect labelling of 
> R1/C1.
>
> As others have said, no effect without cause.

actually it's an IEEE trans paper. I am willing to bet you have never
even written a paper let along had a full one in IEEE.

Hardy
=========================================
What the fuck does what I've done have to do with you "don't
think this is just phase-advance, but common sense tells you it
must be"?
I've explained it to you, if you have problem with the explanation
then says so, otherwise stick your sour grapes up your arse.
I'm willing to bet you don't think at all.






0
7/9/2011 9:05:10 AM
On Jul 9, 9:05=A0pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
wrote:
> "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> news:b70a5b34-3783-46c1-b19b-02191f337b77@t7g2000vbv.googlegroups.com...
> On Jul 9, 7:37 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
> wrote:
>
>
>
> > "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> >news:19f8dc7e-7cc4-485b-aaa0-aa89369e9de1@h8g2000yqj.googlegroups.com...
> > On Jul 9, 2:22 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
> > wrote:
>
> > > "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> > >news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com=
....
> > > |http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> > > |
> > > | They appear to get an output before there is an input! Surely some
> > > | mistake...
> > > |
> > > |
> > > |
> > > | Hardy
>
> > > OMG! Current leads voltage in a capacitor! Who'd a thunk it?
> > > Fig 7 shows a square wave input, but fig 8 is not square and
> > > therefore not the input as claimed. Fig. 6 has two resistors both
> > > labelled R1 and two capacitors both labelled C1, those guys
> > > must have had too much saki.
>
> > I thought a lot about this, and I don't think this is just phase-
> > advance, but common sense tells you it must be.
> > What is not clear is the 2 LEDs in teh circuit, is the second one
> > supposed to light before the first?
>
> > Hardy
>
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > Sure, no reason it shouldn't.
> > step 1: circuit is steady state.
> > step 2: delta V appears across the non-inverting input and inverting
> > input.
> > step 3: through amplification the output LED lights.
> > step 4: through the feedback capacitor the "input" LED lights.
> > step 5: circuit reverts to steady state as there is no DC in the feedba=
ck
> > to the non-inverting input but there is to the inverting input, R3.
> > step 6: the output LED extinguishes.
> > step 7: the "input" LED extinguishes.
>
> > The "input" LED actually gets its power from the arse end of the op-amp=
,
> > not from any input source. Fig 7 doesn't show that.
>
> > This is just some students scratching out a term paper, obviously anyon=
e
> > can
> > duplicate their results. I'd deduct marks for incorrect labelling of
> > R1/C1.
>
> > As others have said, no effect without cause.
>
> actually it's an IEEE trans paper. I am willing to bet you have never
> even written a paper let along had a full one in IEEE.
>
> Hardy
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> What the fuck does what I've done have to do with you "don't
> think this is just phase-advance, but common sense tells you it
> must be"?
> I've explained it to you, if you have problem with the explanation
> then says so, otherwise stick your sour grapes up your arse.
> I'm willing to bet you don't think at all.

Because you're talking complete bollocks! It's a phase-advance
circuit.
Your heath-robinson up a bit down a bit explanation is a red herring
and of no use to the central argument.
The circuit is in fact a form of predictor and the output of the pulse
is before the input as claimed.(but not uncausal).
It's not current leading voltage, it's voltage phase-shifted to be
more positive than the input. as claimed, the group delay is in fact
negative. For example, if you take a pure time-advance exp(jwT) then
this has unity magnitude and a positive linear slope for phase. (wT).
Over a limited freq range this is what they have  (their amplitude is
not constant however ).

To overcome this problem one can do the following.

Take a pure integrator and put a pure time-delay exp(-jwt) in the
feedback path. For high-enough gain at low frequencies only, the
closed-loop transfer function will (by the action of feedback and high
gain) be approx exp(+jwt). Of course you must maintain stability which
doesn't give you much bandwidth to work with at all. If you then try
and stabilise the circuit, you need phase-advance which cancels out
the phase-delay of the time-delay. If you put a sine-wave in you get
an output which appears to be before the input. This is just a
predictor of sorts, but deterministic. It's not uncausal since the
output only appears to be advanced in time on the scope just as with
the case of a phase-advance (for a single sine wave). As the authors
point out, it is "anticipation".


Hardy

0
gyansorova (941)
7/9/2011 3:14:36 PM
Phil Hobbs wrote:

> HardySpicer wrote:
>> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>>
>> They appear to get an output before there is an input! Surely some
>> mistake...
> 
> 
> Unfortunately they found it had already been reported in last month's
> journal. ;)
> 
> I once wasted an entire day trying to do that (back when I was 21 or
> so).  These guys don't seem to have got the memo about causality.
> 
> Love to see them build one that works.

1) Publish questionable research.
2) Seek funds for commercial project base upon #1.
3) Advertise 'negative group delay' speaker cables on Amazon.
4) ?????
5) Profit!

-- 
Paul Hovnanian     mailto:Paul@Hovnanian.com
------------------------------------------------------------------
6 out of 7 dwarfs are not happy.

0
Paul261 (1126)
7/9/2011 3:26:44 PM
"HardySpicer" <gyansorova@gmail.com> wrote in message 
news:2607763a-b077-442a-a1ef-a2e43d40ac1f@m22g2000yqh.googlegroups.com...
On Jul 9, 9:05 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
wrote:
> "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> news:b70a5b34-3783-46c1-b19b-02191f337b77@t7g2000vbv.googlegroups.com...
> On Jul 9, 7:37 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
> wrote:
>
>
>
> > "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> >news:19f8dc7e-7cc4-485b-aaa0-aa89369e9de1@h8g2000yqj.googlegroups.com...
> > On Jul 9, 2:22 pm, "Androcles" <Headmas...@Hogwarts.physics.June.2011>
> > wrote:
>
> > > "HardySpicer" <gyansor...@gmail.com> wrote in message
>
> > >news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
> > > |http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> > > |
> > > | They appear to get an output before there is an input! Surely some
> > > | mistake...
> > > |
> > > |
> > > |
> > > | Hardy
>
> > > OMG! Current leads voltage in a capacitor! Who'd a thunk it?
> > > Fig 7 shows a square wave input, but fig 8 is not square and
> > > therefore not the input as claimed. Fig. 6 has two resistors both
> > > labelled R1 and two capacitors both labelled C1, those guys
> > > must have had too much saki.
>
> > I thought a lot about this, and I don't think this is just phase-
> > advance, but common sense tells you it must be.
> > What is not clear is the 2 LEDs in teh circuit, is the second one
> > supposed to light before the first?
>
> > Hardy
>
> > ===========================================
> > Sure, no reason it shouldn't.
> > step 1: circuit is steady state.
> > step 2: delta V appears across the non-inverting input and inverting
> > input.
> > step 3: through amplification the output LED lights.
> > step 4: through the feedback capacitor the "input" LED lights.
> > step 5: circuit reverts to steady state as there is no DC in the 
> > feedback
> > to the non-inverting input but there is to the inverting input, R3.
> > step 6: the output LED extinguishes.
> > step 7: the "input" LED extinguishes.
>
> > The "input" LED actually gets its power from the arse end of the op-amp,
> > not from any input source. Fig 7 doesn't show that.
>
> > This is just some students scratching out a term paper, obviously anyone
> > can
> > duplicate their results. I'd deduct marks for incorrect labelling of
> > R1/C1.
>
> > As others have said, no effect without cause.
>
> actually it's an IEEE trans paper. I am willing to bet you have never
> even written a paper let along had a full one in IEEE.
>
> Hardy
> =========================================
> What the fuck does what I've done have to do with you "don't
> think this is just phase-advance, but common sense tells you it
> must be"?
> I've explained it to you, if you have problem with the explanation
> then says so, otherwise stick your sour grapes up your arse.
> I'm willing to bet you don't think at all.

Because you're talking complete bollocks!
==============================

Oh, ok. The circuit output occurs before the input and causality
is denied. Happy now?

*plonk*

Do not reply to this generic message, it was automatically generated;
you have been kill-filed, either for being boringly stupid, repetitive,
unfunny, ineducable, repeatedly posting politics, religion or off-topic
subjects to a sci. newsgroup, attempting cheapskate free advertising
for profit, because you are a troll, because you responded to George
Hammond the complete fruit cake, simply insane or any combination
or permutation of the aforementioned reasons; any reply will go unread.

Boringly stupid is the most common cause of kill-filing, but because
this message is generic the other reasons have been included. You are
left to decide which is most applicable to you.

There is no appeal, I have despotic power over whom I will electronically
admit into my home and you do not qualify as a reasonable person I would
wish to converse with or even poke fun at. Some weirdoes are not kill-
filed, they amuse me and I retain them for their entertainment value
as I would any chicken with two heads, either one of which enables the
dumb bird to scratch dirt, step back, look down, step forward to the
same spot and repeat the process eternally.

This should not trouble you, many of those plonked find it a blessing
that they are not required to think and can persist in their bigotry
or crackpot theories without challenge.

You have the right to free speech, I have the right not to listen. The
kill-file will be cleared annually with spring cleaning or whenever I
purchase a new computer or hard drive.
 Update: the last clearance was 19/08/10. Some individuals have been
restored to the list.

I'm fully aware that you may be so stupid as to reply, but the purpose
of this message is to encourage others to kill-file fuckwits like you.

I hope you find this explanation is satisfactory but even if you don't,
damnly my frank, I don't give a dear. Have a nice day and fuck off.







0
7/9/2011 3:48:49 PM
On 09/07/2011 02:30, HardySpicer wrote:
> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
> They appear to get an output before there is an input! Surely some
> mistake...
>
>
> Hardy

Depends what you mean by "output" and "input". It's not a mistake in the 
paper. Here is a quote..

"One may think that making use of this twist it is possible to send 
information to the past despite of the causality. Of course this is wrong"

They go on to explain why it's wrong.




0
7/9/2011 5:17:40 PM
Androcles wrote:
> "HardySpicer" <gyansorova@gmail.com> wrote in message 
> news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
> | http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> |
> | They appear to get an output before there is an input! Surely some
> | mistake...
> |
> |
> |
> | Hardy
> 
> OMG! Current leads voltage in a capacitor!  Who'd a thunk it?
> Fig 7 shows a square wave input, but fig 8 is not square and
> therefore not the input as claimed. Fig. 6 has two resistors both
> labelled R1 and two capacitors both labelled C1, those guys
> must have had too much saki.
> 
> 

I think you've missed the point, which is not the phase
relationship of E and I in a capacitor.
Figure 8 shows the input to the _negative delay circuit_.
What's wrong with having 2 R1's & 2 C1's to show that they
have identical values in that paper?
                    OR
If you were making a comment meant to be humor, then I missed
*your* point.  If so, I apologize.

Ed
0
ehsjr1 (6)
7/9/2011 7:52:36 PM
"ehsjr" <ehsjr@nospamverizon.net> wrote in message 
news:ivabi1$bb5$1@news.eternal-september.org...
| Androcles wrote:
| > "HardySpicer" <gyansorova@gmail.com> wrote in message
| > 
news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
| > | http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
| > |
| > | They appear to get an output before there is an input! Surely some
| > | mistake...
| > |
| > |
| > |
| > | Hardy
| >
| > OMG! Current leads voltage in a capacitor!  Who'd a thunk it?
| > Fig 7 shows a square wave input, but fig 8 is not square and
| > therefore not the input as claimed. Fig. 6 has two resistors both
| > labelled R1 and two capacitors both labelled C1, those guys
| > must have had too much saki.
| >
| >
|
| I think you've missed the point, which is not the phase
| relationship of E and I in a capacitor.
| Figure 8 shows the input to the _negative delay circuit_.

There is no such animal as a "negative delay", and Fig 8 shows
the trace on an oscilloscope, NOT any "input".


| What's wrong with having 2 R1's & 2 C1's to show that they
| have identical values in that paper?

For the very obvious reason that the output drives the voltage at
at the junction of C1 and R1 and now you have no idea which
junction I'm referring to, that's what wrong. What's wrong with
calling "LED in" and "LED out" just "LED" to show they have
identical colours in Fig 7, and why are LED and LED not shown
connected to R1 and C1 in Fig 6?




0
7/9/2011 8:54:20 PM
On Jul 9, 11:26=A0am, "Paul Hovnanian P.E." <p...@hovnanian.com> wrote:

> > Love to see them build one that works.
>
> 1) Publish questionable research.
> 2) Seek funds for commercial project base upon #1.
> 3) Advertise 'negative group delay' speaker cables on Amazon.
> 4) ?????
> 5) Profit!

No problem.

1. Publish "research" linking negative group delay to global warming.

2. Mysterious money suddenly pouring in.

3. Use up money to create paper proving beyond doubt that climate
change is linked to CO2 through negative group delays.

4. Rinse and repeat. Rinse and repeat. etc.


0
bjacoby (27)
7/9/2011 9:14:07 PM
On Fri, 8 Jul 2011 18:30:37 -0700 (PDT), HardySpicer
<gyansorova@gmail.com> wrote:

>http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>
>They appear to get an output before there is an input! Surely some
>mistake...
>
>
>
>Hardy


What they're holding back is that the circuit is dependant on using
devices where the substrates have been doped with recently developed
componds incorporating thio-timoliine-

 http://danm.ucsc.edu/~phoenix/danm203/thiotimoline.pdf

H.
0
7/9/2011 11:27:09 PM
On 7/9/2011 4:27 PM, Howard Eisenhauer wrote:
> On Fri, 8 Jul 2011 18:30:37 -0700 (PDT), HardySpicer
> <gyansorova@gmail.com>  wrote:
>
>> http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
>>
>> They appear to get an output before there is an input! Surely some
>> mistake...
>>
>>
>>
>> Hardy
>
>
> What they're holding back is that the circuit is dependant on using
> devices where the substrates have been doped with recently developed
> componds incorporating thio-timoliine-
>
>   http://danm.ucsc.edu/~phoenix/danm203/thiotimoline.pdf
>
> H.


Linear phase digital filters routinely deal with negative time.
All that is needed is enough total delay in the sampling process to 
allow casuality.

See < http://www.tinaja.com/glib/muse107.pdf >

-- 
Many thanks,

Don Lancaster                          voice phone: (928)428-4073
Synergetics   3860 West First Street   Box 809 Thatcher, AZ 85552
rss: http://www.tinaja.com/whtnu.xml   email: don@tinaja.com

Please visit my GURU's LAIR web site at http://www.tinaja.com
0
don117 (203)
7/10/2011 4:45:06 AM
Androcles wrote:
> "ehsjr" <ehsjr@nospamverizon.net> wrote in message 
> news:ivabi1$bb5$1@news.eternal-september.org...
> | Androcles wrote:
> | > "HardySpicer" <gyansorova@gmail.com> wrote in message
> | > 
> news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
> | > | http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
> | > |
> | > | They appear to get an output before there is an input! Surely some
> | > | mistake...
> | > |
> | > |
> | > |
> | > | Hardy
> | >
> | > OMG! Current leads voltage in a capacitor!  Who'd a thunk it?
> | > Fig 7 shows a square wave input, but fig 8 is not square and
> | > therefore not the input as claimed. Fig. 6 has two resistors both
> | > labelled R1 and two capacitors both labelled C1, those guys
> | > must have had too much saki.
> | >
> | >
> |
> | I think you've missed the point, which is not the phase
> | relationship of E and I in a capacitor.
> | Figure 8 shows the input to the _negative delay circuit_.
> 
> There is no such animal as a "negative delay", and Fig 8 shows
> the trace on an oscilloscope, NOT any "input".

Figure 8 shows the traces labeled "output" and "input".
Did you miss that? Or are you objecting to the ellipsis?

See figure 7.  Do you see the words "Negative delay circuit"?
Figure 8 shows the input and the output pulses of that circuit.
You have to read with some understanding.  The filters will
make the square wave pulses look like the waveforms in the figure.


> 
> 
> | What's wrong with having 2 R1's & 2 C1's to show that they
> | have identical values in that paper?
> 
> For the very obvious reason that the output drives the voltage at
> at the junction of C1 and R1 and now you have no idea which
> junction I'm referring to, 

Well, with you talking and exhibiting zero understanding, you're
right.  I have no idea what _you_ have in mind.

If you wanted to be clear you could've used one of these:
The voltage at junction of R1 and R1.
The voltage at the non-inverting input to the op amp.

However, the paper is not intended to be a tutorial on Bessel
filters.  There is no need to study the filter at all.  All you
need to know is the input and output wave shapes.

> that's what wrong. What's wrong with
> calling "LED in" and "LED out" just "LED" 

Apparently the names they used carry no meaning for you.
They identify the input and output sides of the "Negative delay
circuit".

> to show they have
> identical colours in Fig 7, and why are LED and LED not shown
> connected to R1 and C1 in Fig 6?

You don't know electronics? Or you didn't read it carefully?
Or you're a troll?

Figure 6 is labeled "2nd-order Bessel low pass filter"
The LEDs are not connected to it.

The LEDs are show directly connected at the input and the
output of the "Negative delay circuit".  There is a cable
(or wire) connection from the output of the filter section
to the input of the delay section.

There is *no* connection of any LED to "R1 and C1 in Fig 6"

I'm sorry, but I have the impression that you either don't know
enough electronics to understand where your point of view is
amiss, or that you aren't properly reading the sections of the
paper that you refer to, or that you're just trolling.

Ed



> 
> 
> 
> 
0
ehsjr1 (6)
7/10/2011 6:24:56 AM
"ehsjr" <ehsjr@nospamverizon.net> wrote in message 
news:ivbgjk$g22$1@news.eternal-september.org...
| Androcles wrote:
| > "ehsjr" <ehsjr@nospamverizon.net> wrote in message
| > news:ivabi1$bb5$1@news.eternal-september.org...
| > | Androcles wrote:
| > | > "HardySpicer" <gyansorova@gmail.com> wrote in message
| > | >
| > 
news:f66954fb-a6b5-4f36-9e4b-cc4140803426@x16g2000yqg.googlegroups.com...
| > | > | http://www.kuee.kyoto-u.ac.jp/~kitano/paper/slp2/slp2.pdf
| > | > |
| > | > | They appear to get an output before there is an input! Surely some
| > | > | mistake...
| > | > |
| > | > |
| > | > |
| > | > | Hardy
| > | >
| > | > OMG! Current leads voltage in a capacitor!  Who'd a thunk it?
| > | > Fig 7 shows a square wave input, but fig 8 is not square and
| > | > therefore not the input as claimed. Fig. 6 has two resistors both
| > | > labelled R1 and two capacitors both labelled C1, those guys
| > | > must have had too much saki.
| > | >
| > | >
| > |
| > | I think you've missed the point, which is not the phase
| > | relationship of E and I in a capacitor.
| > | Figure 8 shows the input to the _negative delay circuit_.
| >
| > There is no such animal as a "negative delay", and Fig 8 shows
| > the trace on an oscilloscope, NOT any "input".
|
| Figure 8 shows the traces labeled "output" and "input".
| Did you miss that? Or are you objecting to the ellipsis?
|

Fig 8 does NOT show "the input to the _negative delay circuit_".
Did you hallucinate an oscilloscope trace is a schematic diagram?

| See figure 7.  Do you see the words "Negative delay circuit"?

I know bullshit when I see it, yes. I try not to step in it or it
sticks to my shoe and spreads a stink everywhere.
There is no such animal as a "negative delay", and Fig 8 shows
the trace on an oscilloscope, NOT any "input".
Look at fig 6, and tell me where the LEDs are connected.
Output, pin 6. That's fine for one of them.
The other LED:
Pin 2?  Not a chance.
Pin 3?  Not a chance.
Real input, R1? Not for that trace.
Junction of R1 and R1.
In other words it is connected to the output, pin 6, in series with C1.
Fig 7 is a LIE.

| Figure 8 shows the input and the output pulses of that circuit.

No it doesn't. Figure 8 shows the output and the secondary
delayed output (which is then connected back to the input via R1).


| You have to read with some understanding.  The filters will
| make the square wave pulses look like the waveforms in the figure.


I understand there is no such animal as "negative delay". You have
to know bullshit when it stinks.

|
| >
| >
| > | What's wrong with having 2 R1's & 2 C1's to show that they
| > | have identical values in that paper?
| >
| > For the very obvious reason that the output drives the voltage at
| > at the junction of C1 and R1 and now you have no idea which
| > junction I'm referring to,
|
| Well, with you talking and exhibiting zero understanding, you're
| right.  I have no idea what _you_ have in mind.
|
| If you wanted to be clear you could've used one of these:
| The voltage at junction of R1 and R1.

Bwhahahaha!
If I wanted to be clear I'd follow convention and wouldn't have two R1s.
Kitano, Nakanishi and Sugiyama don't want to be clear, they want to
spread bullshit, like you.


| The voltage at the non-inverting input to the op amp.

Same as the voltage at the inverting input (to within a microvolt or so).

| However, the paper is not intended to be a tutorial on Bessel
| filters.  There is no need to study the filter at all.  All you
| need to know is the input and output wave shapes.
|
What input wave shape? I can only see the two output wave shapes,
from pin 6 and from C1-R1 junction.



| > that's what wrong. What's wrong with
| > calling "LED in" and "LED out" just "LED"
|
| Apparently the names they used carry no meaning for you.

That's right. They are "LEDout" and "LEDout via C1", "LED in"
has no meaning.



| They identify the input and output sides of the "Negative delay
| circuit".

No such animal exists.


|
| > to show they have
| > identical colours in Fig 7, and why are LED and LED not shown
| > connected to R1 and C1 in Fig 6?
|
| You don't know electronics? Or you didn't read it carefully?

I designed test equipment for Marconi Avionics in the '70s-- 
Concorde, Tornado, Lynx, Boeing 747 autothrottle.

| Or you're a troll?

Or you are a name-calling gullible and ignorant cunt?


| Figure 6 is labeled "2nd-order Bessel low pass filter"
| The LEDs are not connected to it.

It must be wonderful to say what they NOT connected to,
maybe they are connected your elbow to your arse?


|
| The LEDs are show directly connected at the input and the
| output of the "Negative delay circuit".

Where? Pin 2? Pin 3? C1? C1? R1? R1? Pin 6?
You don't know electronics? Or you didn't read it carefully?


 There is a cable
| (or wire) connection from the output of the filter section
| to the input of the delay section.
|
| There is *no* connection of any LED to "R1 and C1 in Fig 6"
|
So the entire paper is bullshit. The LED isn't connected anywhere.


| I'm sorry, but I have the impression that you either don't know
| enough electronics to understand where your point of view is
| amiss, or that you aren't properly reading the sections of the
| paper that you refer to, or that you're just trolling.
|
You are a sorry idiot if you believe in negative delays, time does
not run backwards; or you are a gullible and ignorant cunt.



0
7/10/2011 7:55:39 AM
On Jul 10, 7:55=A0pm, "Androcles" <Headmas...@Hogwarts.physics.June.
2011> wrote:

> You are a sorry idiot if you believe in negative delays, time does
> not run backwards; or you are a gullible and ignorant cunt.

Over your head I am afraid! Having a negative delay does not mean time
runs backwards at all!
As somebody pointed out, in digital filters we quite often have -ve
delay to make an uncausal filter causal. (that's a symmetric FIR
filter).
An overall time-delay prevents the "Tardis" effect you are worried
about.

Idiot (as Uncle Al would have said to you!)

Hardy
0
gyansorova (941)
7/10/2011 6:57:08 PM
On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
<gyansorova@gmail.com> wrote:

>On Jul 10, 7:55�pm, "Androcles" <Headmas...@Hogwarts.physics.June.
>2011> wrote:
>
>> You are a sorry idiot if you believe in negative delays, time does
>> not run backwards; or you are a gullible and ignorant cunt.
>
>Over your head I am afraid! Having a negative delay does not mean time
>runs backwards at all!
>As somebody pointed out, in digital filters we quite often have -ve
>delay to make an uncausal filter causal. (that's a symmetric FIR
>filter).
>An overall time-delay prevents the "Tardis" effect you are worried
>about.
>
>Idiot (as Uncle Al would have said to you!)
>
>Hardy

It's easy to have a negative delay, as long as you have a longer
positive delay first. That's what the paper was about. Silly,
actually.

John

0
jjlarkin (641)
7/10/2011 8:03:48 PM
On Jul 11, 8:03=A0am, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
>
>
>
> <gyansor...@gmail.com> wrote:
> >On Jul 10, 7:55=A0pm, "Androcles" <Headmas...@Hogwarts.physics.June.
> >2011> wrote:
>
> >> You are a sorry idiot if you believe in negative delays, time does
> >> not run backwards; or you are a gullible and ignorant cunt.
>
> >Over your head I am afraid! Having a negative delay does not mean time
> >runs backwards at all!
> >As somebody pointed out, in digital filters we quite often have -ve
> >delay to make an uncausal filter causal. (that's a symmetric FIR
> >filter).
> >An overall time-delay prevents the "Tardis" effect you are worried
> >about.
>
> >Idiot (as Uncle Al would have said to you!)
>
> >Hardy
>
> It's easy to have a negative delay, as long as you have a longer
> positive delay first. That's what the paper was about. Silly,
> actually.
>
> John

but where does the longer positive delay come about in an analogue
filter?
There isn't one other than the propagation time  of the op-amp itself.
This isn't a time advance, it's a phase advance.


Hardy
0
gyansorova (941)
7/10/2011 8:55:18 PM
On Sun, 10 Jul 2011 13:03:48 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
><gyansorova@gmail.com> wrote:
>
>>On Jul 10, 7:55�pm, "Androcles" <Headmas...@Hogwarts.physics.June.
>>2011> wrote:
>>
>>> You are a sorry idiot if you believe in negative delays, time does
>>> not run backwards; or you are a gullible and ignorant cunt.
>>
>>Over your head I am afraid! Having a negative delay does not mean time
>>runs backwards at all!
>>As somebody pointed out, in digital filters we quite often have -ve
>>delay to make an uncausal filter causal. (that's a symmetric FIR
>>filter).
>>An overall time-delay prevents the "Tardis" effect you are worried
>>about.
>>
>>Idiot (as Uncle Al would have said to you!)
>>
>>Hardy
>
>It's easy to have a negative delay, as long as you have a longer
>positive delay first. That's what the paper was about. Silly,
>actually.

I once did a level converter than had a negative delay.  It was right there in
the spec!  The standards required that delay be measured from 50% to 50%.  The
threshold wasn't in the middle, so...
0
krw2 (1128)
7/10/2011 9:09:05 PM
On 7/10/2011 1:55 PM, HardySpicer wrote:
> On Jul 11, 8:03 am, John Larkin
> <jjlar...@highNOTlandTHIStechnologyPART.com>  wrote:
>> On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
>>
>>
>>
>> <gyansor...@gmail.com>  wrote:
>>> On Jul 10, 7:55 pm, "Androcles"<Headmas...@Hogwarts.physics.June.
>>> 2011>  wrote:
>>
>>>> You are a sorry idiot if you believe in negative delays, time does
>>>> not run backwards; or you are a gullible and ignorant cunt.
>>
>>> Over your head I am afraid! Having a negative delay does not mean time
>>> runs backwards at all!
>>> As somebody pointed out, in digital filters we quite often have -ve
>>> delay to make an uncausal filter causal. (that's a symmetric FIR
>>> filter).
>>> An overall time-delay prevents the "Tardis" effect you are worried
>>> about.
>>
>>> Idiot (as Uncle Al would have said to you!)
>>
>>> Hardy
>>
>> It's easy to have a negative delay, as long as you have a longer
>> positive delay first. That's what the paper was about. Silly,
>> actually.
>>
>> John
>
> but where does the longer positive delay come about in an analogue
> filter?
> There isn't one other than the propagation time  of the op-amp itself.
> This isn't a time advance, it's a phase advance.
>
>
> Hardy


That is the beauty of digital filters -- certain types (such as 
symmetric linear phase) do not have analog equivalents.


-- 
Many thanks,

Don Lancaster                          voice phone: (928)428-4073
Synergetics   3860 West First Street   Box 809 Thatcher, AZ 85552
rss: http://www.tinaja.com/whtnu.xml   email: don@tinaja.com

Please visit my GURU's LAIR web site at http://www.tinaja.com
0
don117 (203)
7/10/2011 9:39:45 PM
On Sun, 10 Jul 2011 13:55:18 -0700 (PDT), HardySpicer
<gyansorova@gmail.com> wrote:

>On Jul 11, 8:03�am, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
>>
>>
>>
>> <gyansor...@gmail.com> wrote:
>> >On Jul 10, 7:55�pm, "Androcles" <Headmas...@Hogwarts.physics.June.
>> >2011> wrote:
>>
>> >> You are a sorry idiot if you believe in negative delays, time does
>> >> not run backwards; or you are a gullible and ignorant cunt.
>>
>> >Over your head I am afraid! Having a negative delay does not mean time
>> >runs backwards at all!
>> >As somebody pointed out, in digital filters we quite often have -ve
>> >delay to make an uncausal filter causal. (that's a symmetric FIR
>> >filter).
>> >An overall time-delay prevents the "Tardis" effect you are worried
>> >about.
>>
>> >Idiot (as Uncle Al would have said to you!)
>>
>> >Hardy
>>
>> It's easy to have a negative delay, as long as you have a longer
>> positive delay first. That's what the paper was about. Silly,
>> actually.
>>
>> John
>
>but where does the longer positive delay come about in an analogue
>filter?

They pre-shaped the digital pulse through a lowpass filter, which
added delay and added a leading shoulder - a heads-up warning - before
the delayed peak. The following "negative delay" stage just looks at
the leading shoulder and fakes a new, "earlier" peak. But nothing
happens before the original digital rising edge.


>There isn't one other than the propagation time  of the op-amp itself.
>This isn't a time advance, it's a phase advance.

The peak is advanced in time, but that's no miracle.

John


0
jjlarkin (641)
7/10/2011 11:27:17 PM

wrote in message news:c35k17tgol9imnng0kjk7kuigua1jtqfat@4ax.com...

On Sun, 10 Jul 2011 13:03:48 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
><gyansorova@gmail.com> wrote:
>
>>On Jul 10, 7:55 pm, "Androcles" <Headmas...@Hogwarts.physics.June.
>>2011> wrote:
>>
>>> You are a sorry idiot if you believe in negative delays, time does
>>> not run backwards; or you are a gullible and ignorant cunt.
>>
>>Over your head I am afraid! Having a negative delay does not mean time
>>runs backwards at all!
>>As somebody pointed out, in digital filters we quite often have -ve
>>delay to make an uncausal filter causal. (that's a symmetric FIR
>>filter).
>>An overall time-delay prevents the "Tardis" effect you are worried
>>about.
>>
>>Idiot (as Uncle Al would have said to you!)
>>
>>Hardy
>
>It's easy to have a negative delay, as long as you have a longer
>positive delay first. That's what the paper was about. Silly,
>actually.

I once did a level converter than had a negative delay.  It was right there 
in
the spec!  The standards required that delay be measured from 50% to 50%. 
The
threshold wasn't in the middle, so...

IIRC, the Fairchild 9300 4-bit shift register had a negative delay.  Some 
specsmanship with the clock being measured at 90% and the output at 50%...

   Best wishes,
   --Phil 

0
pomartel (147)
7/12/2011 12:42:58 AM
On Jul 11, 8:42=A0pm, "Phil Martel" <pomar...@comcast.net> wrote:
> wrote in messagenews:c35k17tgol9imnng0kjk7kuigua1jtqfat@4ax.com...
>
> On Sun, 10 Jul 2011 13:03:48 -0700, John Larkin
>
>
>
>
>
>
>
>
>
> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
> ><gyansor...@gmail.com> wrote:
>
> >>On Jul 10, 7:55 pm, "Androcles" <Headmas...@Hogwarts.physics.June.
> >>2011> wrote:
>
> >>> You are a sorry idiot if you believe in negative delays, time does
> >>> not run backwards; or you are a gullible and ignorant cunt.
>
> >>Over your head I am afraid! Having a negative delay does not mean time
> >>runs backwards at all!
> >>As somebody pointed out, in digital filters we quite often have -ve
> >>delay to make an uncausal filter causal. (that's a symmetric FIR
> >>filter).
> >>An overall time-delay prevents the "Tardis" effect you are worried
> >>about.
>
> >>Idiot (as Uncle Al would have said to you!)
>
> >>Hardy
>
> >It's easy to have a negative delay, as long as you have a longer
> >positive delay first. That's what the paper was about. Silly,
> >actually.
>
> I once did a level converter than had a negative delay. =A0It was right t=
here
> in
> the spec! =A0The standards required that delay be measured from 50% to 50=
%.
> The
> threshold wasn't in the middle, so...
>
> IIRC, the Fairchild 9300 4-bit shift register had a negative delay. =A0So=
me
> specsmanship with the clock being measured at 90% and the output at 50%..=
..

I knew a photo processor who had a big negative delay. It could be a
week before I got my pictures back.

Jerry
--
Engineering is the art of making what you want from things you can
get.
0
jya (12871)
7/12/2011 8:21:05 PM
Phil Martel wrote:
> 
> wrote in message news:c35k17tgol9imnng0kjk7kuigua1jtqfat@4ax.com...
> 
> On Sun, 10 Jul 2011 13:03:48 -0700, John Larkin
> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:
> 
> >On Sun, 10 Jul 2011 11:57:08 -0700 (PDT), HardySpicer
> ><gyansorova@gmail.com> wrote:
> >
> >>On Jul 10, 7:55 pm, "Androcles" <Headmas...@Hogwarts.physics.June.
> >>2011> wrote:
> >>
> >>> You are a sorry idiot if you believe in negative delays, time does
> >>> not run backwards; or you are a gullible and ignorant cunt.
> >>
> >>Over your head I am afraid! Having a negative delay does not mean time
> >>runs backwards at all!
> >>As somebody pointed out, in digital filters we quite often have -ve
> >>delay to make an uncausal filter causal. (that's a symmetric FIR
> >>filter).
> >>An overall time-delay prevents the "Tardis" effect you are worried
> >>about.
> >>
> >>Idiot (as Uncle Al would have said to you!)
> >>
> >>Hardy
> >
> >It's easy to have a negative delay, as long as you have a longer
> >positive delay first. That's what the paper was about. Silly,
> >actually.
> 
> I once did a level converter than had a negative delay.  It was right there
> in
> the spec!  The standards required that delay be measured from 50% to 50%.
> The
> threshold wasn't in the middle, so...
> 
> IIRC, the Fairchild 9300 4-bit shift register had a negative delay.  Some
> specsmanship with the clock being measured at 90% and the output at 50%...

;)

The cost of the chip was no doubt dominated by the size of the MOS
capacitor on the clock line, to compensate for the rest of it being
slow.

Cheers

Phil Hobbs
-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
0
2/11/2012 7:04:31 PM
getting the output before the input can be perfectly physical.
Now usually it means that my amplifier decided to become an oscillator.
0
2/13/2012 5:54:04 AM
Reply:

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