US-TX-Austin: Silicon Design Eng., 6yrs exp., Verilog, IC design tool flows, UNI (45331657608)
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Position:     Silicon Design Eng.
Reference:    SMC01773
Location:     Austin TX
Duration:     Perm

Skills:       6yrs of total industry experience
              Silicon project and/or architecture leadership experience
              An in-depth knowledge of communications systems and IC�s
              A solid understanding of Verilog or similar language
              Prior experience in a communications or related IC
              development environment
              Knowledgeable with standard IC design tool flows
              In-depth knowledge in synthesis and static timing analysis
              tools
              Experience working on a UNIX or LINUX platform
              Excellent communication skills


Scope:        Digital design engineer. Activities include architecture and
              implementation of complex circuits for wireless
              communications ASICs.
              Responsibilities:
              Actively participating in the definition and implementation
              of communication ASICs Architecture and specification
              definition. Implementation and debug Methodology definition

Our Client:   Competitive base salary
              Stock options
              Annual performance reviews
              U.S. Benefits:


              Comprehensive medical and dental health care plans
              (employees & dependents)
              Life insurance
              Dependent life insurance
              Accidental death and dismemberment insurance
              Short term disability
              401K plan
              12 FTO (Flexible Time Off) days/year
              10 paid holidays


Please send your current resume in confidence to <staffing@eurosoft-inc.com>

..45331657608.