US-TX-Austin: Sr. Digital Design Eng.; Verilog RTL Codiig, Chip-level verificati (45335157608)
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Position:     SR Digital Design Eng.
Reference:    SMC01824
Location:     Austin TX
Duration:     Perm

Skills:       Architectural Definition
              Verilog RTL coding
              Chip-level verification and/or behavioral modeling
              Synthesis
              DFT
              Static Timing Analysis
              Experience with mixed signal design
              DSP
              Custom circuit design
              High speed design
              Min. 8 years industry background
              Master�s a plus, EE a must


Scope:        Design engineer with a complete working knowledge of digital
              design processes


Please send your current resume in confidence to <staffing@eurosoft-inc.com>

..45335157608.