US-TX-Austin: Sr. Verification Eng., 3-8yrs exp., Verilog, SOC design, DSP, Audi (45332932403)
Position: Sr. Verification Eng.
Location: Austin TX
Skills: BSEE (MSEE preferred) with experience ranging from 3-8
Applicants should have skills in the following areas:
Mixed-signal SOC design verification and simulation tools
DSP architectures, synthesis tools, and Audio signal
Communications knowledge and experience with bus interface
units is considered a plus.
Scope: Member of small team of verification engineers developing
and implementing Verification plans on large DSP and ARM
core based SOC devices. Write block and SOC level test
benches and environments using Verilog, System Verilog,
C/C++, Specman e, and Vera. Work closely with software,
applications, and chip design groups to support verification
and validation efforts. Designs may include DSP and ARM
cores, filter elements, digital to analog converter
processing blocks, state machines, and bus interface units.
The proven ability to create, evaluate, debug, and improve a
verification process is essential for this position.
Please send your current resume in confidence to <email@example.com>
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