US--CA--San Jose -- Physical Design Engineer

Physical Design Engineer and CAD

5+ years of experience in high performance ASIC or custom chip design.
This position has both design and support components. Engineer will
participate in place-and-route design tasks, as well as supporting
chip design CAD flow, libraries and IP on a Multi Processor DSP chip.

This engineer will have extensive experience in chip physical design
methodology, flows and tools such as LVS/DRC, Place & Route,
Extraction, Timing closure; must be experienced in working with
backend IP: gds, netlist, lef, def, lib views of standard and custom
cells; and have excellent Unix and scripting skills. Knowledge of
Cadence back-end tools required. BSEE+ or CSE+ required.  For
consideration send resume to joe.connell@comcast.net
6/7/2004 11:59:03 PM
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