US--CA--San Jose -- Verification Engineer

Verification Engineer

Verification Engineer will be responsible for verifying complex
Multi-processor SoC's as well as maintaining and enhancing current
verification environment. Responsibilities will include writing
multiprocessor directed tests in Assembly and Verilog, enhancing and
maintaining random test generators (RTPG), creating PLI and Perl
scripts for daily regression environments, generating and analyzing
RTL code and toggle coverage reports, and maintaining bug tracking
system. This position requires experience with Verilog RTL simulators
and waveform based debugging tools.

Engineer must be fluent in assembly and C languages and must be self
starter. PCI and Ethernet knowledge is a plus. Position requires BS
EE/CS , MS preferred with minimum of 7 years of design verification
experience. For consideration send resume to joe.connell@comcast.net
6/7/2004 11:57:24 PM
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