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Question about non-temporal data prefetch and temporal prefetch.
Hi,
Based on the explanation of Intel IA32 Optimization manual, the data which
are not used again should use non-temporal prefetch instruction, i.e
prefetchnta. The data which will be reused should use temporal prefetch
instruction, i.e. prefetcht0/prefetcht1/prefetct2. Prefetchnta will fetch
the data into SELECTED WAYS OF L2 cache. Prefetcht0/t1/t2 will also fetch
the data into L2 cache.
But I didn't see any difference between this non-temporal and temporal
instruction. Nor did I see figure out the direct reason I can connect these
instructions to the concepts of non-temporal and temporal.
Intel IA32 manual says these prefetch instructions are just kind of hint to
the CPU, what is the real meaning of HINT here?
Can anyone give me a more reasonable explanation?
Thanks,
Liang
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Liang
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3/12/2006 8:57:06 PM |
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> But I didn't see any difference between this non-temporal and temporal
> instruction. Nor did I see figure out the direct reason I can connect these
> instructions to the concepts of non-temporal and temporal.
The prefetch instructions have different implementations based on which
processor you are using. Some processors, like the Pentium III,
prefetchnta will fetch it into first level cache, and set the line
dirty in level 2, whereas a prefetch0 will load it into first and
second level.
I believe that on the pentium IV and xeons, all of these prefetch
instructions fetch into the second level of cache. Maybe with one of
the three cache-level'd chips have different implementations of these
instructions.
> Intel IA32 manual says these prefetch instructions are just kind of hint to
> the CPU, what is the real meaning of HINT here?
First, they mean "hint" as in... it's not an instruction... therefore
the processor doesn't have to listen to you. There are times when the
processor completely ignores this request (like, I imagine, when the
load/store channels are already fully).
Second, it means that's entirely processor specific and implementation
defined. This means that it differs from processor to processor and
you, as a programmer, cannot be certain of what it has or hasn't done.
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ldb
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3/13/2006 2:38:37 PM
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1 Replies
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