Is there any Intel document about performing a TLB shootdown on SMP machines ?
If not, any other reliable source for a TLB shootdown implementation ?

John Marcus wrote:

> Is there any Intel document about performing a TLB shootdown on SMP machines ?
> If not, any other reliable source for a TLB shootdown implementation ?

Would a TLB shootdown involve the INVLPG instruction?

-- 
Regards, Grumble

John Marcus wrote:

> Is there any Intel document about performing a TLB shootdown on SMP machines ?
> If not, any other reliable source for a TLB shootdown implementation ?

(I wonder where my other message went.)

I've seen references to "TLB shootdown" in FreeBSD code. You could ask 
on the developer mailing list. You might also try an OS-related 
newsgroup, such as alt.os.development

-- 
Regards, Grumble

On 2004-10-25 11:25:25 -0600, spamtrap@crayne.org (John Marcus) said:

> Is there any Intel document about performing a TLB shootdown on SMP machines ?
> If not, any other reliable source for a TLB shootdown implementation ?

When the OS kernel alters a page table entry (PTE) in memory (by 
storing a new value to it), the copy of the PTE in the TLB (Translation 
Lookaside Buffer) is not altered and is therefore stale. The kernel 
invalidates the target PTE by executing the INVLPG instruction using 
the linear (i.e., virtual) address of the page. The next attempted 
access to any location within the target virtual page will therefore 
miss the TLB, causing the processor's paging unit to walk the address 
translation tables in memory and read the updated PTE into the TLB.

While the execution of the INVLPG instruction fixed the problem on the 
one processor, it has no effect on stale copies of the PTE that may 
reside in the TLBs within other processor cores. This problem is solved 
by:
1. Placing a small program in memory that contains the INVLPG 
instruction with the operand set to the target virtual page address.
2. The kernel code points one of the entries in the IDT (Interrupt 
Descriptor Table) to that code fragment.
3. The kernel code then instructs the Local APIC on the core it is 
executing on to send an IPI (Inter Processor Interrupt) message to the 
local APICs of the other processors. This message contains the vector 
of the IDT entry.
4. Upon receipt of the IPI message, the Local APICs interrupt the 
programs executing on the other cores and they all execute the program, 
thereby "shooting down" their stale copies of the target TLB PTE copy.