Is the macro expansion of the following code defined in SystemVerilog and
if so, what is the expected macro expansion?


`define TEST(x,y) \
   `ifdef TEST_STUFF \
        x <= y + 42; \
   `else \
        x <= y * 53; \
    `define TEST_STUFF \
   `endif

module grmbl(input wire clk,
     input wire [31:0] test,test2,
     output reg [31:0] o1, o2);
   always @(posedge clk) begin
      `TEST(o1,test);
      `TEST(o2,test2);
   end
endmodule


ModelSim expands this as follows, which looks fairly reasonable to me:

module grmbl(input wire clk,
     input wire [31:0] test,test2,
     output reg [31:0] o1, o2);
   always @(posedge clk) begin
                     o1 <= test * 53;            ;
                     o2 <= test2 + 42;    ;
   end
endmodule


Precision Synthesis seems to expand it in the same manner as well, but it
gives the following warnings:

Warning: [42044]: Compiler directive `ifdef is present inside macro definition.
Warning: [42044]: Compiler directive `else is present inside macro definition.
Warning: [42044]: Compiler directive `endif is present inside macro definition.


So, I'm beginning to wonder whether the behavior of this situation is actually
defined.

/Andreas

hi Andreas,

On Mar 18, 11:36=A0am, Andreas Ehliar wrote:
> Is the macro expansion of the following code defined in SystemVerilog and
> if so, what is the expected macro expansion?
>
> `define TEST(x,y) \
> =A0 =A0`ifdef TEST_STUFF \
> =A0 =A0 =A0 =A0 x <=3D y + 42; \
> =A0 =A0`else \
> =A0 =A0 =A0 =A0 x <=3D y * 53; \
> =A0 =A0 `define TEST_STUFF \
> =A0 =A0`endif

The 1800-2009 LRM clearly says that macros can be used inside
`defines, and that they will be substituted AFTER the `define is
expanded - NOT at the point at which it's defined.  However, I
couldn't find anything about the behaviour of directives inside
`define.

It might be safer to turn the whole thing inside-out, with two
different definitions of TEST, even though it's likely to be more
verbose:

`ifdef TEST_STUFF
  `define TEST(x,y)  x <=3D y + 42;
`else
  `define TEST(x,y)  x <=3D y * 53;
  `define TEST_STUFF
`endif

Anyone else know more precisely what's intended by the LRM?
--
Jonathan Bromley