Hi All - I noticed the website for Icarus Verilog (www.icarus.com)
appears to be down.
Does anyone know if/when it will be back up?
IIRC, Steve's currently on vacation abroad so maybe his machine
crashed. I'm sure someone's mirrored his tarballs/binaries somewhere.
A mirror copy is in:
(Thanks google :-) )
> Hi All - I noticed the website for Icarus Verilog (www.icarus.com)
> appears to be down.
> Does anyone know if/when it ...Icarus Verilog #3
I try to understand how it is working for 2 specific cases.
It has a grammatical rule :
statement -> ...
| K_if '(' expression ')' statement_opt %prec
| K_if '(' expression ')' statement_opt K_else statement_opt
As far as I know from compilers theory (and Left to Right Bottom Up
parsing, as also Icarus Verilgo it is), the above rule should throw
conflict, because, the 2 options of the rule have the same prefix
(e.g. s -> s1 ) ( | s1 s2)
However icarus is a tool, that wo...$save in Icarus Verilog
Can I save the state of a simulation using Icarus Verilog simulator?
I found the $save command in Google, but it doen't seem to work in
$save1: This task not defined by any modules. I cannot compile it.
ta_test: Program not runnable, 1 errors.
Any alternatives in Icarus?
On Thu, 23 Jul 2009 07:31:31 -0700, Kenneth Brun Nielsen wrote:
> Can I save the state of a simulation using Icarus Verilog simulator?
> I found the $save command in Google, but it doen't seem to work in
> Icarus (vvp).
> "...icarus verilog 42975
Does anybody knows why does the Icarus Verilog disapeared?
> Does anybody knows why does the Icarus Verilog disapeared?
Not sure! As for me , I would *never* use a synthesizer that was not
supported in some way for any serious. Not to trash the hard work that
was put into Icarus Verilog. Its hard enough trying to track down my own
bugs, let alone somebody elses.
Some things are worth paying for a *team* of engineers to do.
That being said, having free tools are nice. But this is a non-issue
now. I think just about all of the majo...Icarus Verilog for Windows
I will be maintaining recent snapshots of the Icarus Verilog compiler
for the Windows platform in easy to use installers at
http://armoid.com/icarus/. I have been doing this for more than a year
now for the people in my company so I thought, what the heck, for the
same effort I can benefit other users out there.
If you have other free related goodies that can be posted there
--like Verilog test files, utility scripts, etc.-- please email me at
Thanks for Stephen Williams for putting together such a nice Verilog
compiler for...Icarus Verilog #2
I wanted to know if the latest snapshot of iverilog is working with n-
dimensional arrays (n > 1).
...Icarus Verilog opinions
I've been trying out the Icarus Verilog compiler/simulator. It
looks nice so far. Any views on it?
Also, it claims that it can generate code to load onto real
FPGA's. Can it really do that? Has anyone tried it? I'm
interested in Altera devices.
>I've been trying out the Icarus Verilog compiler/simulator. It
>looks nice so far. Any views on it?
>Also, it claims that it can generate code to load onto real
>FPGA's. Can it really do that? Has anyone tried it? I'm
>interested in Altera devices.
I tried its VPI (c interface) and i...Force in Verilog (Icarus)
I'm trying to make a FORCE statement work in Icarus, but it gives me
I want to force a value to a node deep into a hierarchy. The force
statement works on the value itself, but it has no effect on
subsequent calculations. E.g. if I force the input of a simple gate
somewhere in the hierarchy, I would expect its output to change value
to satisfy whatever input->output relation that might exist.
I made the following code for a simple example:
`timescale 1ns / 1ns
force...icarus verilog error
I'm fairly new to verilog and I'm getting a strange error when I'm
compiling my code.
During compilation it just outputs: "Segmentation Fault", without
mentioning anything about what module or line it's occurring.
Anyone know any common mistakes that could cause such an error?
-----BEGIN PGP SIGNED MESSAGE-----
> I'm fairly new to verilog and I'm getting a strange error when I'm
> compiling my code.
> During compilation it just outputs: "Segmentation...Synthesis with Icarus Verilog
I really like the idea of using Icarus Verilog as a Synthesis tool in
our FPGA flow.
I have only used it with a few small test cases.
What's the largest most complex design that you have successfully
using Icarus? How much of a headache was it getting the design
How steep is the learning curve if you are accustomed to other
...Icarus Verilog 356968
I just wanted to get a heads up from anyone out there about this tool.
My initial results (for some trivial designs) were pretty good with the
Has anyone used this for any large synthesis tasks? Any general
comments about usability? Has anyone used this tool in a full design flow?
...$fscanf in Icarus verilog?
I have my testbenches written using $fscanf to load the testcases. This is
working fine in Modelsim. Recently i tried to run the test bench in Icarus
verilog and facing problems. The vvp is telling that it could not fine the
$fscanf module. How can i get it working?
> I have my testbenches written using $fscanf to load the testcases. This is
> working fine in Modelsim. Recently i tried to run the test bench in Icarus
> verilog and facing problems. The vvp is telling that it could not fine the
> $fscanf module. How can i get it working?
1. g...icarus verilog simulator
When I use iverilog for compiling structural verilog code that has no
"always" or "initial" blocks, but only wires and "assign" statements,
I get the error:
invalid module item. Did you forget an initial or always ?
Why is this so?
On Mar 10, 1:25 pm, kb33 <kanchan.devarako...@gmail.com> wrote:
> When I use iverilog for compiling structural verilog code that has no
> "always" or "initial" blocks, but only wires and "assign" statements,
> I get the error:
> invalid module item. Did you forg...Monitoring an event monitor
I would like to monitor an event monitor to make sure that I get an alarm
if it's not running. I would like to use SQL statements for this.
Is there a way to determine the current status on an event monitor, using
SQL? - syscat.events doesn't seem to expose the status of the event
"Troels Arvin" <firstname.lastname@example.org> wrote in message
> I would like to monitor an event monitor to make sure that I get an alarm
> if it's not running. I would like to use SQL sta...