f



Counter, synthesize problems

Hi, I have problems with my counter. Sorry for my poor english ;) Register =
should be reset on the posedge of signal x1 and should be increased on the =
posedge of CLOCK. I know that register can be changed only in one always pr=
ocess, but I don't know how do that. The error is:
Line 33: Signal register[11] in unit blagam_o_synteze is connected to follo=
wing multiple drivers:


My code:

module blagam_o_synteze(input x1, input x2,input wire CLOCK,output wire [11=
:0] DATA);

   =20
	  reg [11:0] register;
	  reg ENABLE;
	=20
	initial
	begin
	register <=3D 12'd0;
	ENABLE <=3D 1'd0;
	end
=09
	always @(posedge x1)
	begin
	ENABLE<=3D1;=09
	register <=3D 12'd0;=09

	end
	=09
	always @(posedge CLOCK)
		begin
		if(ENABLE=3D=3D1)
		register <=3D register + 1;
		end
	=09
	=09
		always@(posedge x2)
		begin
		ENABLE<=3D0;
		end

	assign DATA[11:0]=3Dregister[11:0];
 =20
endmodule
0
adacho94
8/19/2016 11:38:27 AM
comp.lang.verilog 3837 articles. 2 followers. Post Follow

4 Replies
162 Views

Similar Articles

[PageSpeed] 37

On Fri, 19 Aug 2016 04:38:27 -0700, adacho94 wrote:

> Hi, I have problems with my counter. Sorry for my poor english ;)
> Register should be reset on the posedge of signal x1 and should be
> increased on the posedge of CLOCK. I know that register can be changed
> only in one always process, but I don't know how do that.

Roughly, this probably could be implemented in silicon, but I'm not sure 
if the problem, as stated, can be coded in verilog.

> My code:
> 
> module blagam_o_synteze(input x1, input x2,input wire CLOCK,output wire
> [11:0] DATA);
> 
> 
> 	  reg [11:0] register;
> 	  reg ENABLE;
> 	 
> 	initial begin register <= 12'd0;
> 	ENABLE <= 1'd0;
> 	end
> 	
> 	always @(posedge x1)
> 	begin ENABLE<=1;
> 	register <= 12'd0;
> 
> 	end
> 		
> 	always @(posedge CLOCK)
> 		begin if(ENABLE==1)
> 		register <= register + 1;
> 		end
> 		
> 		
> 		always@(posedge x2) begin ENABLE<=0;
> 		end
> 
> 	assign DATA[11:0]=register[11:0];
>   
> endmodule

I'm analyzing what you seem to want to do.

CLOCK: it is supposed to be always running, yes? Then you can do 
something like this:

inital
  begin
    x1_assert <= 0;
    x1_assert_prev <= 0;
    x1_xor_synchronizer <= 0;
    x2_assert <= 0;
    x2_assert_prev <= 0;
    x2_xor_synchronizer <= 0;
    ENABLE <= 0;
    register <= 0;
  end

always @(posedge x1)
  begin
    x1_assert <= !x1_assert;
  end

always @(posedge x2)
  begin
    x2_assert <= !x2_assert;
  end

always @(posedge CLOCK)
  begin
    x1_assert_prev <= x1_assert;
    x2_assert_prev <= x2_assert;
    x1_xor_synchronizer <= (x1_assert ^ x1_assert_prev); // beware
    x2_xor_synchronizer <= (x2_assert ^ x2_assert_prev); // beware

    if (x1_xor_synchronizer)
      begin
        ENABLE <= 1;
        register <= 0;
      end
    else
      if (x2_xor_synchronizer)
        ENABLE <= 0;

    if (ENABLE)
      register <= register +1;
  end

Notice the latency between positive clock edges of x1 and x2 and the 
contents of register.

The trick with this implementation is that you make sure everything that 
happens is driven solely by CLOCK. The gates in that domain then need 
information ferried to them from the x1 and x2 domains. Strobes, like I 
did, are good for unidirectional information transfer.

The second, *VERY* important point has to do with the real-world effect 
of setup and hold times. Basically, if one clock domain uses a signal as 
the other clock domain is changing it, undefined behaviour occurs, 
possibly leaving the circuit in an illegal or unrecoverable state. One 
way of handling that is forcing the output of signal use into a single 
flip-flop, like I did. The other way is registering all signals from 
other domains before using them. That is left as an exercise to the 
reader.

Finally, make sure that all assignments to a register happen in a 
controlled if tree, like I did with the if-else here. Otherwise, the 
circuit will attempt to simultaneously assign two values to a register 
resulting in undefined behaviour which could, again, leave the circuit in 
an illegal or unrecoverable state.

I have no idea about the relative or absolute clock rates and phase 
shifts of the various clocks involved. The circuit above could or could 
not behave as expected.
0
Aleksandar
8/20/2016 12:12:44 PM
Thanks, you rescued my life , it works!!!! :)

0
adacho94
8/22/2016 11:06:15 AM
> 	always @(posedge CLOCK)
> 		begin
> 		if(ENABLE==1)
> 		register <= register + 1;
> 		end
> 		
> 		
> 		always@(posedge x2)
> 		begin
> 		ENABLE<=0;
> 		end
> 
> 	assign DATA[11:0]=register[11:0];
>   
> endmodule

Is this supposed to be synthesizable?  I think you just want an asynchronous reset.  I haven't used one in a while, but the synthesizable HDL  goes like this:

always@(posedge CLOCK or posedge x1) 
  if (x1)
    register <= 0;
  else  
    register <= register + 1;

Really, you ought to resync x1 and x2 to CLOCK and then just use a single clock.
0
Kevin
8/25/2016 1:06:17 AM
On Mon, 22 Aug 2016 04:06:15 -0700, adacho94 wrote:

> Thanks, you rescued my life , it works!!!! :)

That's good to know. :)
0
Aleksandar
8/27/2016 2:08:42 PM
Reply: