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Executing a task at the end of simulation?

Hello,
I'm probably overlooking something, because this should be pretty simple.

In my design I have several RAMs and I'd like to save the contents of some =
of them to a file when the simulation is done. The problem I'm having is th=
at the RAMs are implemented in modules, but it is the top-level testbench w=
ho decides it's time to end the simulation.
So what I'm looking for is either
- a way to "hook" the $finish event from a submodule
- a way to invoke a task, defined in a submodule, from the top-level testbe=
nch

I'm using Icarus and I'm not too concerned about portability to other tools=
 (and the code is not meant for synthesis)
Thanks for any help.

M.
0
minexew
6/2/2016 6:35:03 PM
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In article <9ddbe264-c0ed-49dc-ae45-07d0783e325e@googlegroups.com>,
 <minexew@gmail.com> wrote:
>Hello,
>I'm probably overlooking something, because this should be pretty simple.
>
>In my design I have several RAMs and I'd like to save the contents of some 
>of them to a file when the simulation is done. The problem I'm having is 
>that the RAMs are implemented in modules, but it is the top-level testbench
>who decides it's time to end the simulation.  

>So what I'm looking for is either
>- a way to "hook" the $finish event from a submodule
>- a way to invoke a task, defined in a submodule, from the top-level testbench

Are your RAMS all inferred from a common submodule,  i.e. RAM.v or similar?
That'll make things much easier, but not explicitly neccessary.

At all the RAM instances, I'd just add a little code down at the bottom of the
file (normally ifdef'd out for synthesis).  Something like:
`ifdef REPORT_RAM
  initial
  begin
    @ top.myfinish 
      do_my_ram_dump();
  end
`endif

Then replace your top_level $finish with a:
  ...
  -> myfinish;
  #1  // may be unnneccesary
    $finish;

Brute force, but effective, and simple.  Much easier if you have that "RAM.v" 
file - only one edit at the submodule level.  Add a qualifier of some sort to
only report some rams, if neccesary. 

Regards,

Mark



0
gtwrek
6/2/2016 8:23:23 PM
On Friday, 3 June 2016 04:35:05 UTC+10, min...@gmail.com  wrote:
> Hello,
> I'm probably overlooking something, because this should be pretty simple.
>=20
> In my design I have several RAMs and I'd like to save the contents of som=
e of them to a file when the simulation is done. The problem I'm having is =
that the RAMs are implemented in modules, but it is the top-level testbench=
 who decides it's time to end the simulation.
> So what I'm looking for is either
> - a way to "hook" the $finish event from a submodule
> - a way to invoke a task, defined in a submodule, from the top-level test=
bench
>=20
> I'm using Icarus and I'm not too concerned about portability to other too=
ls (and the code is not meant for synthesis)
> Thanks for any help.
>=20
> M.

If you can use system verilog there is a block called "final".
0
Michael
6/7/2016 7:31:34 AM
final begin
    $display("final block");
end
0
UTF
6/7/2016 7:59:34 AM
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