f



FSM problem~

Hi all,=20
Can anyone help me to design FSM circuit ?
I have no idea to design a fsm circuit!

The Function description is:
The FSM will process the input data mc_din[27:0] according to mc_op[3:0]. T=
here are four possible operations about input data: shift, one=E2=80=99s co=
mplement, two=E2=80=99s complement, and ignored. The output data will be re=
peated or changed next is controlled by mc_op[1:0]. The FSM will generate t=
hese control signals to control the data storage flip-flops. You will need =
one stage pipe to store the processed input data. In the other hand, your F=
SM also generate full signal to your proceeding stage to hold output data i=
f data storage is full, and generate the ready signal (mc_dout_rdy) to next=
 stage to inform it the output data is ready until next stage acknowledging=
 (ns_ack).


Signal	            Direction	     Description
clk	             input	     System clock
rst_n	             input	     reset signal, active low
mc_din[27:0]	     input	     input raw data
mc_op[3:0]	     input	     input operation	(instruction)
mc_din_rdy	     input	     input data ready
ns_ack	             input	     The next stage acknowledgement=09
                                     signal
mc_dout[27:0]	     output	     output data
mc_dout_rdy	     output	     output data ready to next stage
mc_surplus [1:0]     output	     data transfer surplus
mc_full	             output	     current stage full signal to preceding    =
                     =20
                                     stage



=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
operation function table
mc_op[3:2]	(decide the result )
00: input data shift 1 bit right
01: do 1=E2=80=99s complement
10: do 2=E2=80=99s complement
11: ignore the input data , (no output) mc_op[1:0] function is also ignored=
clk.


mc_op[1:0]	(control repeat)
00: output the =E2=80=9Cinput raw data=E2=80=9D 1 time
01: output the =E2=80=9Cinput raw data=E2=80=9D 1 time and =E2=80=9Cresult =
data=E2=80=9D 1 time
10: output the =E2=80=9Cinput raw data=E2=80=9D 1 time and =E2=80=9Cresult =
data=E2=80=9D 2 times
11: output the =E2=80=9D input raw data=E2=80=9D 1 time and =E2=80=9Cresult=
 data=E2=80=9D 3 times
0
syuan1005
12/12/2016 8:35:06 AM
comp.lang.verilog 3837 articles. 2 followers. Post Follow

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On 12/12/2016 3:35 AM, syuan1005@gmail.com wrote:
> Hi all, Can anyone help me to design FSM circuit ? I have no idea to
> design a fsm circuit!

If you don't know what a FSM (finite state machine) is, then you will 
not understand any code given to you.  Have you read the text book on 
FSMs?  The first thing you need to do is to draw a state transition 
diagram.  Once you have that it is easy to translate that into code. 
Until you can turn the verbal description below into a state transition 
diagram you should not even try to write code.


> The Function description is: The FSM will process the input data
> mc_din[27:0] according to mc_op[3:0]. There are four possible
> operations about input data: shift, one’s complement, two’s
> complement, and ignored. The output data will be repeated or changed
> next is controlled by mc_op[1:0]. The FSM will generate these control
> signals to control the data storage flip-flops. You will need one
> stage pipe to store the processed input data. In the other hand, your
> FSM also generate full signal to your proceeding stage to hold output
> data if data storage is full, and generate the ready signal
> (mc_dout_rdy) to next stage to inform it the output data is ready
> until next stage acknowledging (ns_ack).
>
>
> Signal	            Direction	     Description clk	             input
> System clock rst_n	             input	     reset signal, active low
> mc_din[27:0]	     input	     input raw data mc_op[3:0]	     input
> input operation	(instruction) mc_din_rdy	     input	     input data
> ready ns_ack	             input	     The next stage acknowledgement
> signal mc_dout[27:0]	     output	     output data mc_dout_rdy
> output	     output data ready to next stage mc_surplus [1:0]
> output	     data transfer surplus mc_full	             output
> current stage full signal to preceding stage
>
>
>
> ============================================================================
>
>
operation function table
> mc_op[3:2]	(decide the result ) 00: input data shift 1 bit right 01:
> do 1’s complement 10: do 2’s complement 11: ignore the input data ,
> (no output) mc_op[1:0] function is also ignoredclk.
>
>
> mc_op[1:0]	(control repeat) 00: output the “input raw data” 1 time
> 01: output the “input raw data” 1 time and “result data” 1 time 10:
> output the “input raw data” 1 time and “result data” 2 times 11:
> output the ” input raw data” 1 time and “result data” 3 times
>


-- 

Rick C
0
rickman
12/12/2016 4:50:09 PM
Reply: