f



generate/genvar, for loop and procdural (always/initial) block

Dear Community,

I'm fairly new to Verilog and I'm already hitting some hurdles using
the 'genvar' statement.
I have written 2 verilog modules, both of them are using for loops.
though the for loop index is required to be genvar when used out of
always/initial block.
This is my example:

1. The loop index is genvar, the compile fails otherwise:

module rkXor (xout, xin1, xin2);
  parameter width = 4;
  output [1:width] xout;
  input [1:width] xin1, xin2;
  genvar i;
  for ( i = 1; i <= width; i=i+1 )
      assign  xout[i] = xin1[i] ^ xin2[i];
endmodule

2. The loop index is integer, the compile would complain otherwise:

module clock1(clock);
  parameter period = 20;
  parameter nbBits = 4;
  output [0:nbBits-1] clock;
  reg [0:nbBits-1] clock;
  integer i,j;
  initial begin
    for (i = 0; i < nbBits; i=i+1) begin: loop1
      clock[i] = 0;
    end
  end
  always
  begin
    for (j = 0; j < nbBits; j=j+1) begin: loop2
      #(period/2) clock[j] = 1;
      #(period/2) clock[j] = 0;
    end
  end
endmodule

Can someone shed some light on this please ? i.e. why the loop is
behaving differently when used in the always/initial bloc ?

Thank you very much in advance,
Regards,
Riad.
0
Riad
11/4/2009 7:46:21 PM
comp.lang.verilog 3837 articles. 2 followers. Post Follow

10 Replies
8578 Views

Similar Articles

[PageSpeed] 29

On Nov 4, 2:46=A0pm, Riad KACED <riad.ka...@gmail.com> wrote:
> Dear Community,
>
> I'm fairly new to Verilog and I'm already hitting some hurdles using
> the 'genvar' statement.
> I have written 2 verilog modules, both of them are using for loops.
> though the for loop index is required to be genvar when used out of
> always/initial block.
> This is my example:
>
> 1. The loop index is genvar, the compile fails otherwise:
>
> module rkXor (xout, xin1, xin2);
> =A0 parameter width =3D 4;
> =A0 output [1:width] xout;
> =A0 input [1:width] xin1, xin2;
> =A0 genvar i;
> =A0 for ( i =3D 1; i <=3D width; i=3Di+1 )
> =A0 =A0 =A0 assign =A0xout[i] =3D xin1[i] ^ xin2[i];
> endmodule
>
> 2. The loop index is integer, the compile would complain otherwise:
>
> module clock1(clock);
> =A0 parameter period =3D 20;
> =A0 parameter nbBits =3D 4;
> =A0 output [0:nbBits-1] clock;
> =A0 reg [0:nbBits-1] clock;
> =A0 integer i,j;
> =A0 initial begin
> =A0 =A0 for (i =3D 0; i < nbBits; i=3Di+1) begin: loop1
> =A0 =A0 =A0 clock[i] =3D 0;
> =A0 =A0 end
> =A0 end
> =A0 always
> =A0 begin
> =A0 =A0 for (j =3D 0; j < nbBits; j=3Dj+1) begin: loop2
> =A0 =A0 =A0 #(period/2) clock[j] =3D 1;
> =A0 =A0 =A0 #(period/2) clock[j] =3D 0;
> =A0 =A0 end
> =A0 end
> endmodule
>
> Can someone shed some light on this please ? i.e. why the loop is
> behaving differently when used in the always/initial bloc ?
>
> Thank you very much in advance,
> Regards,
> Riad.

Welcome to verilog. Your life will be much easier if you get into the
habit of thinking like how the hardware works as opposed to writing
"code" in software. Your first module is better written as:

module rkXor #(parameter WIDTH =3D 4) (xout, xin1, xin2);
  output [WIDTH-1:0] xout;
  input [WIDTH-1:0] xin1, xin2;

  assign xout[WIDTH-1:0] =3D xin1[WIDTH-1:0] ^ xin2[WIDTH-1:0];
endmodule

The conventional notation for signals, register is MSB:LSB. And we
start from 0.

Others can correct me, but I think I've only ever used genvar in
generate/endgenerate blocks where I want to instantiate the same
modules with different bit-selects of a signals. Because you didn't
use generate/endgenerate block the compile failed. In this case, there
isn't a need to use it. Verilog is very good in understanding "bits"
provided you specify them.

You should spend some time understanding how the "assign" statement
works. I like to think of it as continuous evaluation. An event is
scheduled to update the output when the inputs change.

In your second case, you can declare clock as reg [3:0] clock. Then,
to initialize it to 0 at t=3D0 of simulation,

initial begin
  clock[3:0] =3D 4'b0000;


Initial blocks execute only once at the beginning of simulation.
Always blocks execute each time the specified condition is true. I
prefer to specify the sensitivity list or use always @(*). A better
way might be to use the verilog mode for Emacs and use always @(/
*AUTOSENSE*/) and let the mode generate the sensitivity list for you.
You should look into that.

One way to generate a clock is as follows:

  // generate clock
   reg clk;
   parameter CLOCK_PERIOD =3D 10;
   initial
     clk <=3D 1'b0;
   always #(CLOCK_PERIOD/2) clk =3D ~clk;

Hope this helps.
-1
pallav
11/4/2009 8:42:02 PM
On Nov 4, 2:46=A0pm, Riad KACED <riad.ka...@gmail.com> wrote:
> Dear Community,
>
> I'm fairly new to Verilog and I'm already hitting some hurdles using
> the 'genvar' statement.
> I have written 2 verilog modules, both of them are using for loops.
> though the for loop index is required to be genvar when used out of
> always/initial block.
> This is my example:
>
> 1. The loop index is genvar, the compile fails otherwise:
>
> module rkXor (xout, xin1, xin2);
> =A0 parameter width =3D 4;
> =A0 output [1:width] xout;
> =A0 input [1:width] xin1, xin2;
> =A0 genvar i;
> =A0 for ( i =3D 1; i <=3D width; i=3Di+1 )
> =A0 =A0 =A0 assign =A0xout[i] =3D xin1[i] ^ xin2[i];
> endmodule
>

I'm surprised that this compiles as shown.  What compiler are
you running?  I would assume you needed a generate statement
like:
generate
 genvar i;
 for ( i =3D 1; i <=3D width; i=3Di+1 ) begin : BLOCK_NAME
       assign  xout[i] =3D xin1[i] ^ xin2[i];
 end
endgenerate

That is unless you take the other suggestion of coding it
without a loop.

> 2. The loop index is integer, the compile would complain otherwise:
>
> module clock1(clock);
> =A0 parameter period =3D 20;
> =A0 parameter nbBits =3D 4;
> =A0 output [0:nbBits-1] clock;
> =A0 reg [0:nbBits-1] clock;
> =A0 integer i,j;
> =A0 initial begin
> =A0 =A0 for (i =3D 0; i < nbBits; i=3Di+1) begin: loop1
> =A0 =A0 =A0 clock[i] =3D 0;
> =A0 =A0 end
> =A0 end
> =A0 always
> =A0 begin
> =A0 =A0 for (j =3D 0; j < nbBits; j=3Dj+1) begin: loop2
> =A0 =A0 =A0 #(period/2) clock[j] =3D 1;
> =A0 =A0 =A0 #(period/2) clock[j] =3D 0;
> =A0 =A0 end
> =A0 end
> endmodule
>
> Can someone shed some light on this please ? i.e. why the loop is
> behaving differently when used in the always/initial bloc ?
>
> Thank you very much in advance,
> Regards,
> Riad.

There's a very good reference book from Doulos called the
Verilog Golden Reference Guide.  It describes how the
generate works and how loops inside a generate statement
are different from loops in a procedural block.

Regards,
Gabor
0
gabor
11/4/2009 8:55:57 PM
Hi Pallv,

Thank you very much indeed for your prompt answer.
Well, your comments are very interesting. They don't help me that much
with understanding my problem though.

Both modules I have provided did not use any generate/endgenerate.
Though, one module has worked not the other. the generate/endgenerate
is not required as far as I understand. In fact, I have just read the
following from the Verilog-D IEEE Std 1364-2005 doc (Page 181):

"The keywords generate and endgenerate may be used in a module to
define a generate region. A generate region is a textual span in the
module description where generate constructs may appear. Use of
generate regions is optional. There is no semantic difference in the
module when a generate region is used. A parser may choose to
recognize the generate region to produce different error messages for
misused generate construct keywords ..."
Besides, I'm rather a user of Verilog-AMS where the generate is an
obsolete statement that is left for legacy reasons. This is another
story, I'm just interested in Verilog-D right here.

My guess is that a the for loop behaves differently when in a
procedural bloc like initial/always. That's what I'm trying to
understand.
Anyway, thanks for your advice on the other bits of my code.

Cheers,
Riad.
0
Riad
11/4/2009 9:10:48 PM
Hi Gabor,

My code compiles, yes it does. One of the compilers I have run was
Cadence's ncvlog
Thanks for the reference, I'll try to get hold of it ...

Thanks for your help too !
Cheers,
Riad.
0
Riad
11/4/2009 9:21:23 PM
On Nov 4, 4:10=A0pm, Riad KACED <riad.ka...@gmail.com> wrote:
> Well, your comments are very interesting. They don't help me that much
> with understanding my problem though.
>

Hi Riad,

Looks like I did not understand your question. Sorry.

Kind regards.
0
pallav
11/4/2009 10:51:49 PM
Hi Palav,

Although it didn't really answer my question, your comments are still
very valuable and I'm very grateful for it !
Looking forward for some more people to comment this item !

Cheers,
Riad.
0
Riad
11/5/2009 7:12:07 PM
On Nov 5, 2:12=A0pm, Riad KACED <riad.ka...@gmail.com> wrote:
> Although it didn't really answer my question, your comments are still
> very valuable and I'm very grateful for it !
> Looking forward for some more people to comment this item !

I think what you're missing is the distinction between code that's
"executed" at compile/elaboration time and code that runs at
simulation time (or run time). Obviously, I'm just talking about
simulation here; synthesis also has compile/elaboration time, but
doesn't support initial blocks, so I assume you're interested in
simulation at this point.

Side note: I apologize for lumping compilation and elaboration
together. They're technically different stages, one following the
other, but I don't have the differences at the tip of my brain right
now. They might be discussed in your simulator manual and should be in
the LRM. Reading up on them will help you here.

Generate statements are handled at compile/elaboration time. Your
first example is a generate-for and, being handled at comp/elab time,
it's a useful shorthand for putting down multiple module
instantiations, continuous assigns, or even whole sequential blocks (I
think), with some reference (bit, bit range, array location) varying
with the genvar. Essentially, generate-for statements are to save you
potentially lots of typing, but in theory you could unroll the loop
yourself because the loop count must be known in advance. You're using
it to create more code or structures that will go through compile/
elaboration and then simulation.

Your second example has two sequential blocks containing for loops.
These are not generate-for statements, they're sequential for
statements (I guess you'd call them that). As such, these are handled
at simulation time, and while I hate to put it this way, you can think
of them like a for loop in C -- that is, they can have a variable loop
count, the loop can be interrupted, etc., but most important, you're
not creating new structures, you're running a block of code multiple
times.

As others have mentioned, your generate-for to create multiple 1-bit
assignments is better (and more efficiently) replaced by a single
multi-bit assign, and there are better styles for clock generators.
Personally, I still like this one from Janick Bergeron's _Writing
Testbenches_, 1st ed.:

reg clk;
initial
   forever begin
      #(period/2) clk =3D 1'b0;
      #(period/2) clk =3D 1'b1;
   end

Clock events at time 0 used to cause problems though the simulation
vendors have cleaned those up. I still like delaying the first posedge
clk though. Makes it easier to see what happens on the first clock in
waves.

-cb
0
Chris
11/6/2009 4:01:16 PM
On Nov 6, 11:01=A0am, Chris Briggs <ch...@engim.com> wrote:

[snip]

> . . . there are better styles for clock generators.
> Personally, I still like this one from Janick Bergeron's _Writing
> Testbenches_, 1st ed.:
>
> reg clk;
> initial
> =A0 =A0forever begin
> =A0 =A0 =A0 #(period/2) clk =3D 1'b0;
> =A0 =A0 =A0 #(period/2) clk =3D 1'b1;
> =A0 =A0end
>
> Clock events at time 0 used to cause problems though the simulation
> vendors have cleaned those up. I still like delaying the first posedge
> clk though. Makes it easier to see what happens on the first clock in
> waves.
>
> -cb

That's pretty useful, thanks.  No edge at time zero but X-0
edge at period/2 is still a "negedge" event consistent with
the clock's operation.  I've been using the Xilinx GUI to
generate a quick starter for testbenches, but they always
fill in all the module inputs in an initial block starting
at time zero.  Not a problem for rising edge only clocks
when setting the initial to 0.  Of course the Xilinx stuff
has other start-up issues like their semi-hidden GSR net
that resets all their structural models (but not your
behavioral code) for the first 100 ns of the simulation.

Most of my behavioral code is written with asynchronous
reset, so what happens on the first clock isn't so important.
However I do remember having some headaches with the falling
edge event at time zero due to the initial statement.  I always
thought that "initial" was for initial conditions - i.e.
everything is assumed to start from there, but of course
the LRM says otherwise, i.e. everything is X until initialized
and that X to whatever transition is an event.

Regards,
Gabor
0
gabor
11/6/2009 7:33:41 PM
Gabor wrote:
> everything is X until initialized
> and that X to whatever transition is an event.

Yes, but be very afraid.... Since 2001 you have been
able to initialize module-level variables:

  module foo;
    reg clock = 0;
    always #5 clock = ~clock;
  ...

But that reg-initialization is, by definition, exactly
equivalent to

  reg clock;
  initial clock = 0;

with the semantics that Gabor indicated - clock is
initially X but is changed to 0 as one of the many
things that happens at time 0.  This is, of course,
a fine way to get lots of unpleasant races.

In SystemVerilog-2005, the meaning of that initialization
was redefined to be like a VHDL signal initialization:
the reg had that value since before the Big Bang, and
has no value-change event at time 0.  With the soon-to-
happen merging of Verilog and SystemVerilog, this will
be the generally mandated behaviour.

It happens that most simulator vendors, trying to give
customers roughly what they expect, have implemented
register-initializers in such a way that there will be
no noticeable difference when the new rules kick in.
The de-facto behaviour is one of the legal orderings
of the Verilog code anyway, so the change will not be
disruptive.  But it's as well to be very, very cautious
about what happens around time 0 and, as far as possible,
make your design and testbench completely immune to
time-0 races.  Easier said than done :-(
--
Jonathan Bromley


0
Jonathan
11/7/2009 10:07:01 AM
Hi Guys,

Thank you all for your time and very valuable comments on my query !
Very much appreciated,

Riad.
0
Riad
11/17/2009 5:41:06 PM
Reply:

Similar Artilces:

about the always block in verilog
always @(negedge nrst or posedge PCLK or negedge begin) begin ... end So,how can i determine what event does really happen in begin end block?? On 2/23/2013 8:38 AM, yu zhou wrote: > always @(negedge nrst or posedge PCLK or negedge begin) > begin > ... > end > > So,how can i determine what event does really happen in begin end block?? > You can't. You can only test the current state of the variables in the sensitivity list. Luckily this isn't generally necessary for common synthesis constructs, and my guess is that anything w...

Synthesizing generate and always blocks...
I have a verilog file that has a generate block, followed by a couple of always blocks. The synthesis tool is not able to synthesize......it just goes on without giving any errors or warnings. Is it legal to have all the three blocks in the same file? Thanks kb33 ...

code generation of initial value block
hi In my model their is initial value block can u tell how it is reflected in code generation .I want that shoud be in specific file what is method for that. ...

combinatorial always blocks + for-loops in XST
All- I'm using Spartan 3 + XST 7.1sp4. In the code below, is there a way to use a combinatorial always block and a for-loop to make it more readable and not take 32 lines of source? -Jeff wire [31:0] a; reg [7:0] b [31:0]; reg [2:0] bit; assign a = { b[31][bit], : : b[10][bit], b[9][bit], b[8][bit], b[7][bit], b[6][bit], b[5][bit], b[4][bit], b[3][bit], b[2][bit], b[1][bit], b[0][bit] }; ...

Need comment on the following Verilog always block
I am revieiwing someone elses code and wanted to know the behaviour of following code. Your comments are greatly appreciated. I normally am familiar with <= type assignment. //Register some of the data coming from other modules for data integrity always @(UsbIfClk) begin if(~Res_N) begin CreateMailboxTest = 1'h0; StopMailboxTest = 1'h0; MailboxDataValid = 1'h0; ResetRxBram = 1'h0; end else begin CreateMailboxTest = MTC_CreateMailboxTest; StopMailboxTest = MTC_StopMailbox...

Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
Hi, i'm using Block Memory Generator 2.1 for a 16bit * 1024 RAM implemented in virtex4 BRAM and want to initialize the data with a *.coe file. But if i dump the data from the *.bit file with "data2mem -d" it doesn't match completely with the data from the *.ceo file. for example: * .ceo file: memory_initialization_radix=16; memory_initialization_vector= FFFF, FFFF, 0201, 0403, 0605, 0807, 1009, ... data2mem dump: 7F FF 7F FF 01 01 02 03 03 05 04 07 09 09 It seems that the Block Memory Generator does a wrong mapping of the 16 bit wide ram into the 16 + 2 wide (due to pari...

Alter generated always to generated by default
I have a table that has an identity column in it. It was created generated always and now I would like (need) it to be generated by default. I tried to use the alter table xx alter column, but I don't know how the set the 'SET DATA TYPE' option on the alter statement. Does anyone know how I can change the column(it's an integer) from generated always to generated by defult? I am runnin DB2 v7 on zSeries. Thanks, Doug ...

declaration and initialization inside initial block
Hi Is it possible in verilog(or verilog 2001) to declare and initialize a register inside a initial block . Nikhil Declarations are always outside of procedural blocks. You could set the default type (Verilog2001 feature - check your tool for info) to reg and the first reference in the initial block without a declaration would effectively declare it. Alternatively, the initial assignment could be made at the register declaration where there is no initial block. reg [11:0] MyReg = 12'head; My simulator recognizes this last form so I've used it here and there in my t...

declaration and initialization inside initial block #2
Hi Is it possible in verilog(or verilog 2001) to declare and initialize a register inside a initial block . Nikhil ...

Multiple non-blocking assigns in always block
In the code below when 'set' is 1, is the next value of 'ff' deterministic? My initial thought was that the LHS of non-blocking assignments can be computed in any order and since there are 2 non- blocking assignments, one assigning 0 and one assigning 1, either value could potentially propagate to 'ff'. However, I also realize that the always block itself is procedural so perhaps there is some ordering of the LHS updates of non-blocking assignments within the same always block. Thanks. always @(posedge clk) begin if(~reset_l) begin ff<=0; en...

Re: "Hi,I'm having problems controlling the Agilent E4422B Signal Generator with Labview. When using the Labview driver functions such as initialize instrument I always get an Error -1074135040
Hi, Brooks. Attached please find the files containing all the information concerning my attempt to control the Agilent E4438C. Hope you can make sense of it and help me. &nbsp; Regards isaac nireport.txt: http://forums.ni.com/attachments/ni/170/191414/1/nireport.txt Capture.spy: http://forums.ni.com/attachments/ni/170/191414/2/Capture.spy CaptureSpy.doc: http://forums.ni.com/attachments/ni/170/191414/3/CaptureSpy.doc Hi, If this driver supports multiple instrument models, then you will probably have to set the model in the default settings in MAX. Regards Ray FarmerMessage Edited by...

procs/blocks
Well, maybe not blocks with blocks but blocks with yield? although right now, I only have a fix for procs with blocks and not blocks with blocks via blocks with yield when a proc block is not in stock... class Proc alias __proc_block_call call alias __proc_block_indexer [] def call(*args, &block) __proc_block_call(*(block.nil? ? args : args << block)) end def [](*args, &block) __proc_block_indexer(*(block.nil? ? args : args << block)) end end ----- usage prc = Proc.new {|arg, proc_block| p arg proc_block[arg] } prc.call("Foo") {|...

How to generate variable labels for same component within a generate loop
Hi, I want to know how to generate variable labels for same component within a loop. The following is the code I am writing: component A port ( ... ); end component; begin for I in 5 to 0 generate xxx : A port map ( ... ); end generate; I don't know how to put variable I into the label xxx. Thank you. Weng On 11 Feb 2006 19:25:06 -0800, "Weng Tianxiang" <wtxwtx@gmail.com> wrote: >Hi, >I want to know how to generate variable labels for same component >within a loop. > >The following is the code I am writing: > >component A port ( > ...

Xilinx System Generator
Hello, I would like to as a question if anyone could help me. I was wondering does anyone ever worked with multiple system generator block in xilinx system generator. I don't know how to make a simulation. I've done this. I created two blocks (subsystems). The first one should work on 133MHz. I put system generator block in this subsystem and I set right properties of the module that this block demands. Another module (subsystem) should work at 40Mhz. this module also contain system generator block with regularly set parameters. both modules are placed in same simulation model file an...

Re: i am having a problem with while loops, i have two while loops, i have a random number generator inside the &quot;inside&quot; loop and i want to read an array outside the &quot;outer&quot;
I think I have a similar problem - I have a while loop with Flat Sequence controlled for loop that produces output. This output needs to be displayed every while loop pass, but I get no output as the while loop feeds back thru a shift register and repeats all the innner funcions without sending the ouput to form new entries in the array. &nbsp; Is there any way we could stop the while loop for a split second (but practically just for no time, so that no time is wasted when it outputs the data)? &nbsp; Or is it a bad approach altogether? &nbsp; Appreciate any advice. &nbsp; kolo...

column "generated always as" generated from multiple columns
Hi, I have a table, something similar to: create table my_table ( id char(32) not null primary key, num integer not null, code varchar(2) not null, name varchar(60) not null, [...] ) Now I need to add another column 'calc_field' of type varchar that is always automatically derived from columns: id, num, code (concatenated) I was trying to do something with concatenation and CAST but it always fails. Even if I try to test my expression with simple select to see generated column, the same expression fails in the 'generated always as' s...

Is a For loop always a no-no?
I realize that many times some form of Mathematica built in array function will do the needed job. Here I have a matrix containing individual data traces in rows y[[i]]. I want to make matrix containing the corresponding derivative signals in rows yd[[i]]. I get this done using the following For loop. Matrix yd has been initialized (it wouldn't work with out it). For[i = 1, i < n, i++, yd[[i]] = Drop[RotateLeft[y[[i]]] - y[[i]], -1]]; I tried the obvious (to me): yd = Drop[RotateLeft[y] -y, -1]; But I get garbage. It seems the whole matrix has been flattened to a singl...

Initializing an array of a structure to default value, does compiler do a loop to initialize?
Lets say I have this structure: typedef struct numbers { double first = 0.0; double second = 0.0; double third = 0.0; } MYVALUES; and I initialize an array of MYVALUES like the following MYVALUES * foo; foo = new MYVALUES [3]; I would expect the following initial values from foo: foo[0].first == 0.0 foo[0].second == 0.0 foo[0].third == 0.0 foo[1].first == 0.0 foo[1].second == 0.0 foo[1].third == 0.0 foo[2].first == 0.0 foo[2].second == 0.0 foo[2].third == 0.0 My question is, how does the compiler initialize these values? Does it run a loop to initialize foo kinda like this? fo...

Verilog Generation
Rumor has it that Productivity Design Tools (www.productive-eda.com) is soon to release a tool that is capable of producing RTL Verilog given a higher-level specification. Any readers know anything about PDT, the SPIRIT standard, or other related tools? What are your thoughts on Electronics System Level (ESL) tools in general? Combinational Logic wrote: > Rumor has it that Productivity Design Tools (www.productive-eda.com) > is soon to release a tool that is capable of producing RTL Verilog > given a higher-level specification. Any readers know anything about > PDT...

FOR loop not looping
I have the below script that uses 2 for loops. for some reason they loop is not looping ! /bin/ksh CURR_PATH='/main/nedcor/flexcube' cd $CURR_PATH for DIR1 in 'WIP' 'INPUT';do echo $DIR1 for DIR in $(find . -name $DIR1);do RESULT=`ls -A $DIR | egrep -v "BKUP|BKP"` echo $DIR echo $RESULT echo $RESULT1 if [ -z "$RESULT" ] ; then echo "No Files found" exit 0 else echo file $RESULT found exit 1 ...

generate for loop
Hi, I sit possible to write something like this: [code] genvar i,j; generate for (i = N;i > 0; i = i - 1) for( j = 0 ; j< i;j = j + 1) begin:dec ...... end endgenerate [\code] Thanks, On Jul 20, 6:28=A0am, bil050 <irinali...@gmail.com> wrote: > Hi, > I sit possible to write something like this: You just did! Actually what you're showing would generate N for loops, not N(N+1)/2 statements from your inner loop. If you want those N(N+1)/2 statements, nest: use two generate for and two ...

Generator not generating
Hi, Although I'm no Python expert, I have written generators in the past that have worked like a charm. Don't know why this one doesn't: **** class App: """ A simple Tk application that plots random lines """ def __init__(self, master): # create the main frame frame =3D Frame(master) frame.pack() # create a canvas within the frame self.canvas =3D Canvas(frame, width=3D400, height=3D400) self.canvas.pack(side=3DTOP) # create a button below the canvas and within the frame ...

Looping Problem (Generating files
Hello All, I have a problem with the program that should generate x number of txt files (x is the number of records in the file datafile.txt). Once I execute the program (see below) only one file (instead of x files) is created. The file created is based on the last record in datafile.txt. The program is as follows: ==================================== #! python HEADER = "This page displays longitude-latitude information" SUBHEADER = "City" for line in open("datafile.txt"): town, latlong = line.split('\t') f = open(town + ".txt", &qu...

while loop in a while loop
Hi All, I have the following situation: while(rs.next()) { //loop1 while(rs2.next()) { //loop 2 } } It seems like loop 2 is only beeing used once. Should I after loop2 put the cursor back to the beginning? if so, how do I do that? Thanks! -- Posted by news://news.nb.nu Steven wrote: > Hi All, > > I have the following situation: > > > while(rs.next()) { //loop1 > > while(rs2.next()) { > //loop 2 > } > > } > The architypal loop (for a List eg ArrayList of Blah objects) is: for(It...

Web resources about - generate/genvar, for loop and procdural (always/initial) block - comp.lang.verilog

The Mahablog
Making the World Safe for Liberalism

Resources last updated: 2/18/2016 9:41:24 AM