f



How to give parameter a variable value in tb?

test.v
module test(
a,b
);
parameter AA = 1;
input a;
output b;
assign b = AA==1'b1 ? a : 0;
endmodule

tb.v
module tb();
parameter PAR_A = 0;
//int width;
//scanf(width);
//if(width == 10)PAR_A=0;
//else if(width == 20)PAR_A=1;

test #(.AA(PAR_A)) (
  .a(1'b1),
  .b()
);
endmodule

I want to sometimes PAR_A = 1, sometimes PAR_A=0, sometimes PAR_A = other value. 
How can I do it ?
The environment support systemveilog, but tb.v cannot be changed to tb.sv.
0
Sand
8/5/2016 8:27:23 AM
comp.lang.verilog 3837 articles. 2 followers. Post Follow

2 Replies
114 Views

Similar Articles

[PageSpeed] 55

On Friday, August 5, 2016 at 4:27:28 AM UTC-4, Sand Glass wrote:
> test.v
> module test(
> a,b
> );
> parameter AA = 1;
> input a;
> output b;
> assign b = AA==1'b1 ? a : 0;
> endmodule
> 
> tb.v
> module tb();
> parameter PAR_A = 0;
> //int width;
> //scanf(width);
> //if(width == 10)PAR_A=0;
> //else if(width == 20)PAR_A=1;
> 
> test #(.AA(PAR_A)) (
>   .a(1'b1),
>   .b()
> );
> endmodule
> 
> I want to sometimes PAR_A = 1, sometimes PAR_A=0, sometimes PAR_A = other value. 
> How can I do it ?
> The environment support systemveilog, but tb.v cannot be changed to tb.sv.

The parameter value must be decided during elaboration. If you're looking for changing its value at run time, then you have to use port instead.

Regards,
Michael
0
michael6866
8/6/2016 7:41:22 AM
Depending on the compiler you're using you can overwrite the params on the command line when you compile it.
0
kingalbert1875
9/8/2016 10:22:30 PM
Reply: