Hello friends..
What I want is do generate a RAM block of size 512X8 with two read
ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
the CORE Generator Tool for all the family of devices available. But
in all attempts, what happened was, I could succesfully generate the
verilog file for the RAM block, but when it was mapped into the
corresponding family of device, it shows a succesful synthesys but I
could see only a line when i generated the schematic. Also, when the
design was implemented, it shows an error

 "ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
not supported in target 'virtex5'."

here, 'dist_mem_gen_v3_4'  is the generated HDL file name.

I tried many devices available in Xilinx, but all shows the same
error. Can anybody suggest me what I can do?? Do I need to specify the
class of device anywhere else other than the Project Options in CORE
Generator and Project Properties in Xilinx ISE?? Please help me.. its
urgent!! Tnx in advance..

On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
> Hello friends..
> What I want is do generate a RAM block of size 512X8 with two read
> ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> the CORE Generator Tool for all the family of devices available. But
> in all attempts, what happened was, I could succesfully generate the
> verilog file for the RAM block, but when it was mapped into the
> corresponding family of device, it shows a succesful synthesys but I
> could see only a line when i generated the schematic. Also, when the
> design was implemented, it shows an error
>
> =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> not supported in target 'virtex5'."
>
> here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> I tried many devices available in Xilinx, but all shows the same
> error. Can anybody suggest me what I can do?? Do I need to specify the
> class of device anywhere else other than the Project Options in CORE
> Generator and Project Properties in Xilinx ISE?? Please help me.. its
> urgent!! Tnx in advance..

I highly recommend not using CoreGen for RAMs.  Instead use inference
to get the size and type of RAM you want.  Look at XST manual for RAM
inference or other synthesis tools manuals for RAM inference if you
are not using XST.

-- Amal

Am 11.01.2010 15:17, schrieb Ashwin:

> What I want is do generate a RAM block of size 512X8 with two read
> ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> the CORE Generator Tool for all the family of devices available. But
> in all attempts, what happened was, I could succesfully generate the
> verilog file for the RAM block, but when it was mapped into the
> corresponding family of device, it shows a succesful synthesys but I
> could see only a line when i generated the schematic. Also, when the
> design was implemented, it shows an error
> 
>  "ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> not supported in target 'virtex5'."
> 
> here, 'dist_mem_gen_v3_4'  is the generated HDL file name.

Another way to infer a memory is to use the Xilinx <Language Templates>
which are accessible in the ISE menu.

Ralf

Ashwin wrote:

> What I want is do generate a RAM block of size 512X8 with two read
> ports and a write port in verilog using Xilinx ISE 10.1. 

I would use a code template and use two block rams
with a common write interface.

http://www.google.com/search?&q=verilog+block+ram+template+xilinx

       -- Mike Treseler

On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
> Hello friends..
> What I want is do generate a RAM block of size 512X8 with two read
> ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> the CORE Generator Tool for all the family of devices available. But
> in all attempts, what happened was, I could succesfully generate the
> verilog file for the RAM block, but when it was mapped into the
> corresponding family of device, it shows a succesful synthesys but I
> could see only a line when i generated the schematic. Also, when the
> design was implemented, it shows an error
>
> =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> not supported in target 'virtex5'."
>
> here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> I tried many devices available in Xilinx, but all shows the same
> error. Can anybody suggest me what I can do?? Do I need to specify the
> class of device anywhere else other than the Project Options in CORE
> Generator and Project Properties in Xilinx ISE?? Please help me.. its
> urgent!! Tnx in advance..

There's nothing wrong with using the Core generator for memory.
You shouldn't add the generated Verilog file to your ISE
project, though.  Add the .xco file from CoreGen.  ISE will
actually get what it needs from the precompiled .NGC file.
Another issue I've seen is if you don't originally generate
the core in your project directory, you'll need to move or
copy the .NGC file there.

Regards,
Gabor

On Jan 12, 4:03=A0am, gabor <ga...@alacron.com> wrote:
> On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
>
>
> > Hello friends..
> > What I want is do generate a RAM block of size 512X8 with two read
> > ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> > the CORE Generator Tool for all the family of devices available. But
> > in all attempts, what happened was, I could succesfully generate the
> > verilog file for the RAM block, but when it was mapped into the
> > corresponding family of device, it shows a succesful synthesys but I
> > could see only a line when i generated the schematic. Also, when the
> > design was implemented, it shows an error
>
> > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> > not supported in target 'virtex5'."
>
> > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > I tried many devices available in Xilinx, but all shows the same
> > error. Can anybody suggest me what I can do?? Do I need to specify the
> > class of device anywhere else other than the Project Options in CORE
> > Generator and Project Properties in Xilinx ISE?? Please help me.. its
> > urgent!! Tnx in advance..
>
> There's nothing wrong with using the Core generator for memory.
> You shouldn't add the generated Verilog file to your ISE
> project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> actually get what it needs from the precompiled .NGC file.
> Another issue I've seen is if you don't originally generate
> the core in your project directory, you'll need to move or
> copy the .NGC file there.
>
> Regards,
> Gabor

Yes, as Gabor has said, there is no problem with using Core Generator.
Just ensure that you add the .xco file generated by Coregen to your
project files and not the .v file. Also, ensure that the .ngc file
generated by Coregen is present in the source directory where all your
synthesizable Verilog files are present. U can copy the .xco and .ngc
files to your source directory if you have saved the Coregen files
somewhere else. You get this error message because ISE failed to find
the .ngc file in your current working directory.

--Sharad
Research Scholar,
Nanyang Technological University, Singapore

On Jan 11, 9:17=A0pm, Amal <akhailt...@gmail.com> wrote:
> On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
>
>
>
>
> > Hello friends..
> > What I want is do generate a RAM block of size 512X8 with two read
> > ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> > the CORE Generator Tool for all the family of devices available. But
> > in all attempts, what happened was, I could succesfully generate the
> > verilog file for the RAM block, but when it was mapped into the
> > corresponding family of device, it shows a succesful synthesys but I
> > could see only a line when i generated the schematic. Also, when the
> > design was implemented, it shows an error
>
> > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> > not supported in target 'virtex5'."
>
> > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > I tried many devices available in Xilinx, but all shows the same
> > error. Can anybody suggest me what I can do?? Do I need to specify the
> > class of device anywhere else other than the Project Options in CORE
> > Generator and Project Properties in Xilinx ISE?? Please help me.. its
> > urgent!! Tnx in advance..
>
> I highly recommend not using CoreGen for RAMs. =A0Instead use inference
> to get the size and type of RAM you want. =A0Look at XST manual for RAM
> inference or other synthesis tools manuals for RAM inference if you
> are not using XST.
>
> -- Amal- Hide quoted text -
>
> - Show quoted text -

Thanx for your comments first!
I reffered the XST manual but I could not find a template that can
generate a RAM with two read ports and a write port. For dual port
RAM, one of the port is acting both as read and write ports. But I
want to use both read ports and the write port at the same time. Is
there any way??

On Jan 12, 1:03=A0am, gabor <gabor@alacron.com> wrote:
> On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
>
>
>
>
> > Hello friends..
> > What I want is do generate a RAM block of size 512X8 with two read
> > ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> > the CORE Generator Tool for all the family of devices available. But
> > in all attempts, what happened was, I could succesfully generate the
> > verilog file for the RAM block, but when it was mapped into the
> > corresponding family of device, it shows a succesful synthesys but I
> > could see only a line when i generated the schematic. Also, when the
> > design was implemented, it shows an error
>
> > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> > not supported in target 'virtex5'."
>
> > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > I tried many devices available in Xilinx, but all shows the same
> > error. Can anybody suggest me what I can do?? Do I need to specify the
> > class of device anywhere else other than the Project Options in CORE
> > Generator and Project Properties in Xilinx ISE?? Please help me.. its
> > urgent!! Tnx in advance..
>
> There's nothing wrong with using the Core generator for memory.
> You shouldn't add the generated Verilog file to your ISE
> project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> actually get what it needs from the precompiled .NGC file.
> Another issue I've seen is if you don't originally generate
> the core in your project directory, you'll need to move or
> copy the .NGC file there.
>
> Regards,
> Gabor- Hide quoted text -
>
> - Show quoted text -

Thanxes for you!
but I am sorry that Im new to these tools. Can you please tell me how
to add these files with my project?? Should I add the .v file along
with these files also??

On Jan 12, 5:49=A0pm, Sharad <sharad....@gmail.com> wrote:
> On Jan 12, 4:03=A0am, gabor <ga...@alacron.com> wrote:
>
>
>
>
>
> > On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > Hello friends..
> > > What I want is do generate a RAM block of size 512X8 with two read
> > > ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> > > the CORE Generator Tool for all the family of devices available. But
> > > in all attempts, what happened was, I could succesfully generate the
> > > verilog file for the RAM block, but when it was mapped into the
> > > corresponding family of device, it shows a succesful synthesys but I
> > > could see only a line when i generated the schematic. Also, when the
> > > design was implemented, it shows an error
>
> > > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> > > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> > > not supported in target 'virtex5'."
>
> > > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > > I tried many devices available in Xilinx, but all shows the same
> > > error. Can anybody suggest me what I can do?? Do I need to specify th=
e
> > > class of device anywhere else other than the Project Options in CORE
> > > Generator and Project Properties in Xilinx ISE?? Please help me.. its
> > > urgent!! Tnx in advance..
>
> > There's nothing wrong with using the Core generator for memory.
> > You shouldn't add the generated Verilog file to your ISE
> > project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> > actually get what it needs from the precompiled .NGC file.
> > Another issue I've seen is if you don't originally generate
> > the core in your project directory, you'll need to move or
> > copy the .NGC file there.
>
> > Regards,
> > Gabor
>
> Yes, as Gabor has said, there is no problem with using Core Generator.
> Just ensure that you add the .xco file generated by Coregen to your
> project files and not the .v file. Also, ensure that the .ngc file
> generated by Coregen is present in the source directory where all your
> synthesizable Verilog files are present. U can copy the .xco and .ngc
> files to your source directory if you have saved the Coregen files
> somewhere else. You get this error message because ISE failed to find
> the .ngc file in your current working directory.
>
> --Sharad
> Research Scholar,
> Nanyang Technological University, Singapore- Hide quoted text -
>
> - Show quoted text -

thanx friend!
Is there any way to generate a RAM block with two read ports and a
write port? I should be able to use all the ports ath the same time
(reading and writing at the same time, I will resolve the same
location access). I reffered the available templates but could find
RAMs with a shared port for wirting and reading (dual port RAMs). Is
there any other way??

On Jan 12, 11:33=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
> On Jan 12, 1:03=A0am, gabor <ga...@alacron.com> wrote:
>
>
>
> > On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > Hello friends..
> > > What I want is do generate a RAM block of size 512X8 with two read
> > > ports and a write port in verilog using Xilinx ISE 10.1. I Have tried
> > > the CORE Generator Tool for all the family of devices available. But
> > > in all attempts, what happened was, I could succesfully generate the
> > > verilog file for the RAM block, but when it was mapped into the
> > > corresponding family of device, it shows a succesful synthesys but I
> > > could see only a line when i generated the schematic. Also, when the
> > > design was implemented, it shows an error
>
> > > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' with
> > > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' is
> > > not supported in target 'virtex5'."
>
> > > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > > I tried many devices available in Xilinx, but all shows the same
> > > error. Can anybody suggest me what I can do?? Do I need to specify th=
e
> > > class of device anywhere else other than the Project Options in CORE
> > > Generator and Project Properties in Xilinx ISE?? Please help me.. its
> > > urgent!! Tnx in advance..
>
> > There's nothing wrong with using the Core generator for memory.
> > You shouldn't add the generated Verilog file to your ISE
> > project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> > actually get what it needs from the precompiled .NGC file.
> > Another issue I've seen is if you don't originally generate
> > the core in your project directory, you'll need to move or
> > copy the .NGC file there.
>
> > Regards,
> > Gabor- Hide quoted text -
>
> > - Show quoted text -
>
> Thanxes for you!
> but I am sorry that Im new to these tools. Can you please tell me how
> to add these files with my project?? Should I add the .v file along
> with these files also??

In the ISE Navigator, from the Project drop-down menu
select "Add source" and browse to the .xco file.  If
this file is not in your project directory, you should
copy the .v and .ngc files to the project directory,
but don't add them to the project.  I have had some
issues with simulation when adding Coregen files to
a project.  Sometimes (at least with ISE 10.1) the
new core is not added to the compile list for Modelsim
until the project has been closed and re-opened.  You
can work around this in ModelSim by opening the file
within Modelsim and compiling it manually.

HTH,
Gabor

On Jan 12, 11:41=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
> On Jan 12, 5:49=A0pm, Sharad <sharad....@gmail.com> wrote:
>
>
>
> > On Jan 12, 4:03=A0am, gabor <ga...@alacron.com> wrote:
>
> > > On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > > Hello friends..
> > > > What I want is do generate a RAM block of size 512X8 with two read
> > > > ports and a write port in verilog using Xilinx ISE 10.1. I Have tri=
ed
> > > > the CORE Generator Tool for all the family of devices available. Bu=
t
> > > > in all attempts, what happened was, I could succesfully generate th=
e
> > > > verilog file for the RAM block, but when it was mapped into the
> > > > corresponding family of device, it shows a succesful synthesys but =
I
> > > > could see only a line when i generated the schematic. Also, when th=
e
> > > > design was implemented, it shows an error
>
> > > > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' wit=
h
> > > > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4' =
is
> > > > not supported in target 'virtex5'."
>
> > > > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > > > I tried many devices available in Xilinx, but all shows the same
> > > > error. Can anybody suggest me what I can do?? Do I need to specify =
the
> > > > class of device anywhere else other than the Project Options in COR=
E
> > > > Generator and Project Properties in Xilinx ISE?? Please help me.. i=
ts
> > > > urgent!! Tnx in advance..
>
> > > There's nothing wrong with using the Core generator for memory.
> > > You shouldn't add the generated Verilog file to your ISE
> > > project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> > > actually get what it needs from the precompiled .NGC file.
> > > Another issue I've seen is if you don't originally generate
> > > the core in your project directory, you'll need to move or
> > > copy the .NGC file there.
>
> > > Regards,
> > > Gabor
>
> > Yes, as Gabor has said, there is no problem with using Core Generator.
> > Just ensure that you add the .xco file generated by Coregen to your
> > project files and not the .v file. Also, ensure that the .ngc file
> > generated by Coregen is present in the source directory where all your
> > synthesizable Verilog files are present. U can copy the .xco and .ngc
> > files to your source directory if you have saved the Coregen files
> > somewhere else. You get this error message because ISE failed to find
> > the .ngc file in your current working directory.
>
> > --Sharad
> > Research Scholar,
> > Nanyang Technological University, Singapore- Hide quoted text -
>
> > - Show quoted text -
>
> thanx friend!
> Is there any way to generate a RAM block with two read ports and a
> write port? I should be able to use all the ports ath the same time
> (reading and writing at the same time, I will resolve the same
> location access). I reffered the available templates but could find
> RAMs with a shared port for wirting and reading (dual port RAMs). Is
> there any other way??

Each block RAM or distributed RAM has only two address buses.
You can have one read/write port and another read only port
for distributed memory, or up to two read/write ports for
block RAM.  You cannot have three independent ports on one
RAM.

However if you need to have two independent read ports and
one write port, you can use two RAM's, tying the write
ports to the same signals so you have two copies of the
same data.  Then you get a read port from each RAM.

Regards,
Gabor

On Jan 12, 11:43=A0pm, gabor <ga...@alacron.com> wrote:
> On Jan 12, 11:41=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
>
>
>
>
> > On Jan 12, 5:49=A0pm, Sharad <sharad....@gmail.com> wrote:
>
> > > On Jan 12, 4:03=A0am, gabor <ga...@alacron.com> wrote:
>
> > > > On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > > > Hello friends..
> > > > > What I want is do generate a RAM block of size 512X8 with two rea=
d
> > > > > ports and a write port in verilog using Xilinx ISE 10.1. I Have t=
ried
> > > > > the CORE Generator Tool for all the family of devices available. =
But
> > > > > in all attempts, what happened was, I could succesfully generate =
the
> > > > > verilog file for the RAM block, but when it was mapped into the
> > > > > corresponding family of device, it shows a succesful synthesys bu=
t I
> > > > > could see only a line when i generated the schematic. Also, when =
the
> > > > > design was implemented, it shows an error
>
> > > > > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4' w=
ith
> > > > > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3_4=
' is
> > > > > not supported in target 'virtex5'."
>
> > > > > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > > > > I tried many devices available in Xilinx, but all shows the same
> > > > > error. Can anybody suggest me what I can do?? Do I need to specif=
y the
> > > > > class of device anywhere else other than the Project Options in C=
ORE
> > > > > Generator and Project Properties in Xilinx ISE?? Please help me..=
 its
> > > > > urgent!! Tnx in advance..
>
> > > > There's nothing wrong with using the Core generator for memory.
> > > > You shouldn't add the generated Verilog file to your ISE
> > > > project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> > > > actually get what it needs from the precompiled .NGC file.
> > > > Another issue I've seen is if you don't originally generate
> > > > the core in your project directory, you'll need to move or
> > > > copy the .NGC file there.
>
> > > > Regards,
> > > > Gabor
>
> > > Yes, as Gabor has said, there is no problem with using Core Generator=
..
> > > Just ensure that you add the .xco file generated by Coregen to your
> > > project files and not the .v file. Also, ensure that the .ngc file
> > > generated by Coregen is present in the source directory where all you=
r
> > > synthesizable Verilog files are present. U can copy the .xco and .ngc
> > > files to your source directory if you have saved the Coregen files
> > > somewhere else. You get this error message because ISE failed to find
> > > the .ngc file in your current working directory.
>
> > > --Sharad
> > > Research Scholar,
> > > Nanyang Technological University, Singapore- Hide quoted text -
>
> > > - Show quoted text -
>
> > thanx friend!
> > Is there any way to generate a RAM block with two read ports and a
> > write port? I should be able to use all the ports ath the same time
> > (reading and writing at the same time, I will resolve the same
> > location access). I reffered the available templates but could find
> > RAMs with a shared port for wirting and reading (dual port RAMs). Is
> > there any other way??
>
> Each block RAM or distributed RAM has only two address buses.
> You can have one read/write port and another read only port
> for distributed memory, or up to two read/write ports for
> block RAM. =A0You cannot have three independent ports on one
> RAM.
>
> However if you need to have two independent read ports and
> one write port, you can use two RAM's, tying the write
> ports to the same signals so you have two copies of the
> same data. =A0Then you get a read port from each RAM.
>
> Regards,
> Gabor- Hide quoted text -
>
> - Show quoted text -

I tried it. I want only a 512X8 RAM block. But modelling in such a
way, as you said, two RAM blocks were generated. I have a doubt that,
instead of 512 locations, it generates 1024 (512+512) locations. The
same copy of data will be written into both the blocks. Is that right?
I could get a write port (common to both RAM blocks) and two read
ports (one each form the two blocks). What I want to ask is, does this
method make an overuse of 512 locations? Is this a limitation to this
model?

On Jan 12, 11:02=A0pm, Ashwin <ashwin.9...@gmail.com> wrote:
> On Jan 12, 11:43=A0pm, gabor <ga...@alacron.com> wrote:
>
>
>
> > On Jan 12, 11:41=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > On Jan 12, 5:49=A0pm, Sharad <sharad....@gmail.com> wrote:
>
> > > > On Jan 12, 4:03=A0am, gabor <ga...@alacron.com> wrote:
>
> > > > > On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > > > > Hello friends..
> > > > > > What I want is do generate a RAM block of size 512X8 with two r=
ead
> > > > > > ports and a write port in verilog using Xilinx ISE 10.1. I Have=
 tried
> > > > > > the CORE Generator Tool for all the family of devices available=
.. But
> > > > > > in all attempts, what happened was, I could succesfully generat=
e the
> > > > > > verilog file for the RAM block, but when it was mapped into the
> > > > > > corresponding family of device, it shows a succesful synthesys =
but I
> > > > > > could see only a line when i generated the schematic. Also, whe=
n the
> > > > > > design was implemented, it shows an error
>
> > > > > > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_4'=
 with
> > > > > > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_v3=
_4' is
> > > > > > not supported in target 'virtex5'."
>
> > > > > > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > > > > > I tried many devices available in Xilinx, but all shows the sam=
e
> > > > > > error. Can anybody suggest me what I can do?? Do I need to spec=
ify the
> > > > > > class of device anywhere else other than the Project Options in=
 CORE
> > > > > > Generator and Project Properties in Xilinx ISE?? Please help me=
... its
> > > > > > urgent!! Tnx in advance..
>
> > > > > There's nothing wrong with using the Core generator for memory.
> > > > > You shouldn't add the generated Verilog file to your ISE
> > > > > project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> > > > > actually get what it needs from the precompiled .NGC file.
> > > > > Another issue I've seen is if you don't originally generate
> > > > > the core in your project directory, you'll need to move or
> > > > > copy the .NGC file there.
>
> > > > > Regards,
> > > > > Gabor
>
> > > > Yes, as Gabor has said, there is no problem with using Core Generat=
or.
> > > > Just ensure that you add the .xco file generated by Coregen to your
> > > > project files and not the .v file. Also, ensure that the .ngc file
> > > > generated by Coregen is present in the source directory where all y=
our
> > > > synthesizable Verilog files are present. U can copy the .xco and .n=
gc
> > > > files to your source directory if you have saved the Coregen files
> > > > somewhere else. You get this error message because ISE failed to fi=
nd
> > > > the .ngc file in your current working directory.
>
> > > > --Sharad
> > > > Research Scholar,
> > > > Nanyang Technological University, Singapore- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > thanx friend!
> > > Is there any way to generate a RAM block with two read ports and a
> > > write port? I should be able to use all the ports ath the same time
> > > (reading and writing at the same time, I will resolve the same
> > > location access). I reffered the available templates but could find
> > > RAMs with a shared port for wirting and reading (dual port RAMs). Is
> > > there any other way??
>
> > Each block RAM or distributed RAM has only two address buses.
> > You can have one read/write port and another read only port
> > for distributed memory, or up to two read/write ports for
> > block RAM. =A0You cannot have three independent ports on one
> > RAM.
>
> > However if you need to have two independent read ports and
> > one write port, you can use two RAM's, tying the write
> > ports to the same signals so you have two copies of the
> > same data. =A0Then you get a read port from each RAM.
>
> > Regards,
> > Gabor- Hide quoted text -
>
> > - Show quoted text -
>
> I tried it. I want only a 512X8 RAM block. But modelling in such a
> way, as you said, two RAM blocks were generated. I have a doubt that,
> instead of 512 locations, it generates 1024 (512+512) locations. The
> same copy of data will be written into both the blocks. Is that right?
> I could get a write port (common to both RAM blocks) and two read
> ports (one each form the two blocks). What I want to ask is, does this
> method make an overuse of 512 locations? Is this a limitation to this
> model?

The limitation to the *hardware* is that you cannot have one write
address and two read addresses that are different from the write
address and use one BlockRAM.

You can share a read/write address, using a write on some cycles and a
read on others.

You can time multiplex your memory such that you write on the "off"
phase of a 2x clock and read on the "proper" phase of that 2x clock,
allowing both read addresses to produce the read data at the same
time.  By multiplexing the write and read address on one port and
using the "DONT_CHANGE" attribute value (or whatever the syntax is for
the value that holds the last read value during a write) your read
port looks like what you expect.

Time multiplexing is one of the most "efficient" ways to add multi-
port capability over the dual-address BlockRAM capabilities if you 1)
have the overhead in speed and 2) don't have extra BlockRAM sitting
around idle just wishing they could be utilized.

It's a little more work over having a hardware 3-address BlockRAM, but
the limitation is in the basic hardware elements.  If you want a
register that works on both edges of the clock, you have to "build" an
equivalent configuration out of the resources you *do* have available;
same with the M-port memories (M>2).

On Jan 13, 6:34=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Jan 12, 11:02=A0pm, Ashwin <ashwin.9...@gmail.com> wrote:
>
>
>
>
>
> > On Jan 12, 11:43=A0pm, gabor <ga...@alacron.com> wrote:
>
> > > On Jan 12, 11:41=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > > On Jan 12, 5:49=A0pm, Sharad <sharad....@gmail.com> wrote:
>
> > > > > On Jan 12, 4:03=A0am, gabor <ga...@alacron.com> wrote:
>
> > > > > > On Jan 11, 9:17=A0am, Ashwin <ashwin.9...@gmail.com> wrote:
>
> > > > > > > Hello friends..
> > > > > > > What I want is do generate a RAM block of size 512X8 with two=
 read
> > > > > > > ports and a write port in verilog using Xilinx ISE 10.1. I Ha=
ve tried
> > > > > > > the CORE Generator Tool for all the family of devices availab=
le. But
> > > > > > > in all attempts, what happened was, I could succesfully gener=
ate the
> > > > > > > verilog file for the RAM block, but when it was mapped into t=
he
> > > > > > > corresponding family of device, it shows a succesful synthesy=
s but I
> > > > > > > could see only a line when i generated the schematic. Also, w=
hen the
> > > > > > > design was implemented, it shows an error
>
> > > > > > > =A0"ERROR NgdBuild:605 - logical root block 'dist_mem_gen_v3_=
4' with
> > > > > > > type 'dist_mem_gen_v3_4' is unexpanded. Symbol 'dist_mem_gen_=
v3_4' is
> > > > > > > not supported in target 'virtex5'."
>
> > > > > > > here, 'dist_mem_gen_v3_4' =A0is the generated HDL file name.
>
> > > > > > > I tried many devices available in Xilinx, but all shows the s=
ame
> > > > > > > error. Can anybody suggest me what I can do?? Do I need to sp=
ecify the
> > > > > > > class of device anywhere else other than the Project Options =
in CORE
> > > > > > > Generator and Project Properties in Xilinx ISE?? Please help =
me.. its
> > > > > > > urgent!! Tnx in advance..
>
> > > > > > There's nothing wrong with using the Core generator for memory.
> > > > > > You shouldn't add the generated Verilog file to your ISE
> > > > > > project, though. =A0Add the .xco file from CoreGen. =A0ISE will
> > > > > > actually get what it needs from the precompiled .NGC file.
> > > > > > Another issue I've seen is if you don't originally generate
> > > > > > the core in your project directory, you'll need to move or
> > > > > > copy the .NGC file there.
>
> > > > > > Regards,
> > > > > > Gabor
>
> > > > > Yes, as Gabor has said, there is no problem with using Core Gener=
ator.
> > > > > Just ensure that you add the .xco file generated by Coregen to yo=
ur
> > > > > project files and not the .v file. Also, ensure that the .ngc fil=
e
> > > > > generated by Coregen is present in the source directory where all=
 your
> > > > > synthesizable Verilog files are present. U can copy the .xco and =
..ngc
> > > > > files to your source directory if you have saved the Coregen file=
s
> > > > > somewhere else. You get this error message because ISE failed to =
find
> > > > > the .ngc file in your current working directory.
>
> > > > > --Sharad
> > > > > Research Scholar,
> > > > > Nanyang Technological University, Singapore- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > thanx friend!
> > > > Is there any way to generate a RAM block with two read ports and a
> > > > write port? I should be able to use all the ports ath the same time
> > > > (reading and writing at the same time, I will resolve the same
> > > > location access). I reffered the available templates but could find
> > > > RAMs with a shared port for wirting and reading (dual port RAMs). I=
s
> > > > there any other way??
>
> > > Each block RAM or distributed RAM has only two address buses.
> > > You can have one read/write port and another read only port
> > > for distributed memory, or up to two read/write ports for
> > > block RAM. =A0You cannot have three independent ports on one
> > > RAM.
>
> > > However if you need to have two independent read ports and
> > > one write port, you can use two RAM's, tying the write
> > > ports to the same signals so you have two copies of the
> > > same data. =A0Then you get a read port from each RAM.
>
> > > Regards,
> > > Gabor- Hide quoted text -
>
> > > - Show quoted text -
>
> > I tried it. I want only a 512X8 RAM block. But modelling in such a
> > way, as you said, two RAM blocks were generated. I have a doubt that,
> > instead of 512 locations, it generates 1024 (512+512) locations. The
> > same copy of data will be written into both the blocks. Is that right?
> > I could get a write port (common to both RAM blocks) and two read
> > ports (one each form the two blocks). What I want to ask is, does this
> > method make an overuse of 512 locations? Is this a limitation to this
> > model?
>
> The limitation to the *hardware* is that you cannot have one write
> address and two read addresses that are different from the write
> address and use one BlockRAM.
>
> You can share a read/write address, using a write on some cycles and a
> read on others.
>
> You can time multiplex your memory such that you write on the "off"
> phase of a 2x clock and read on the "proper" phase of that 2x clock,
> allowing both read addresses to produce the read data at the same
> time. =A0By multiplexing the write and read address on one port and
> using the "DONT_CHANGE" attribute value (or whatever the syntax is for
> the value that holds the last read value during a write) your read
> port looks like what you expect.
>
> Time multiplexing is one of the most "efficient" ways to add multi-
> port capability over the dual-address BlockRAM capabilities if you 1)
> have the overhead in speed and 2) don't have extra BlockRAM sitting
> around idle just wishing they could be utilized.
>
> It's a little more work over having a hardware 3-address BlockRAM, but
> the limitation is in the basic hardware elements. =A0If you want a
> register that works on both edges of the clock, you have to "build" an
> equivalent configuration out of the resources you *do* have available;
> same with the M-port memories (M>2).- Hide quoted text -
>
> - Show quoted text -


Here, I have made a RAM block of size 512X8 with two read and a write
port. I am not sure about the limitation of the design. What I want is
to access all the 3 ports simultaneously. Can anybody help me??

module Data_Mem	(clk, rst, we, rd_addr1, rd_addr2, wr_addr, wr_data,
rd_data1, rd_data2);

`define 	DATA_WIDTH	8
`define	ADDR_LEN		8
`define	RAM_DEPTH		256

input				clk;
input				rst;
input				we;		//	Write enable
input	[`ADDR_LEN-1:0]		rd_addr1;		//	address to read first operand.
input	[`ADDR_LEN-1:0]		rd_addr2;		//	address to read second operand.
input	[`ADDR_LEN-1:0]		wr_addr;		//	address to write the data.
input	[`DATA_WIDTH-1:0]	wr_data;	//	data to be written into the
memory, coming from the ALU.

output	[`DATA_WIDTH-1:0]	rd_data1;		//	first operand read from memory.
output	[`DATA_WIDTH-1:0]	rd_data2;		//	second operand read from
memory.

wire				clk;
wire				rst;
wire				we;
wire	[`ADDR_LEN-1:0]		rd_addr1;
wire	[`ADDR_LEN-1:0]		rd_addr2;
wire	[`ADDR_LEN-1:0]		wr_addr;
wire	[`DATA_WIDTH-1:0]	wr_data;
wire	[`DATA_WIDTH-1:0]	rd_data1;
wire	[`DATA_WIDTH-1:0]	rd_data2;

reg	[`DATA_WIDTH-1:0]	ram	[`RAM_DEPTH-1:0];	//	RAM memory of size
256X8

always @ (posedge clk)
begin
	if (rst)						//	on reset, the following value gets stored in data
memory.
	begin
ram	[	0	]	<=3D	8'd1;
ram	[	1	]	<=3D	8'd1;
ram	[	2	]	<=3D	8'd1;
// like that, it goes.
ram	[	254	]	<=3D	8'd1;
ram	[	255	]	<=3D	8'd1;

	end

	else
		if (we)
			ram[wr_addr]<=3D wr_data;
end



//	Read operation

assign	rd_data1=3D ram[rd_addr1];			//	first data is read from memory
asynchronously.
assign	rd_data2=3D ram[rd_addr2];			//	second data is read from memory
asynchronously.

endmodule

On Jan 13, 11:07=A0pm, Ashwin <ashwin.9...@gmail.com> wrote:
[snip]
> Here, I have made a RAM block of size 512X8 with two read and a write
> port. I am not sure about the limitation of the design. What I want is
> to access all the 3 ports simultaneously. Can anybody help me??
>
> module Data_Mem (clk, rst, we, rd_addr1, rd_addr2, wr_addr, wr_data,
> rd_data1, rd_data2);
>
> `define =A0 =A0 =A0 =A0 DATA_WIDTH =A0 =A0 =A08
> `define ADDR_LEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A08
> `define RAM_DEPTH =A0 =A0 =A0 =A0 =A0 =A0 =A0 256
>
> input =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk;
> input =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst;
> input =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 we; =A0 =A0 =A0=
 =A0 =A0 =A0 // =A0 =A0 =A0Write enable
> input =A0 [`ADDR_LEN-1:0] =A0 =A0 =A0 =A0 rd_addr1; =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 // =A0 =A0 =A0address to read first operand.
> input =A0 [`ADDR_LEN-1:0] =A0 =A0 =A0 =A0 rd_addr2; =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 // =A0 =A0 =A0address to read second operand.
> input =A0 [`ADDR_LEN-1:0] =A0 =A0 =A0 =A0 wr_addr; =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0// =A0 =A0 =A0address to write the data.
> input =A0 [`DATA_WIDTH-1:0] =A0 =A0 =A0 wr_data; =A0 =A0 =A0 =A0// =A0 =
=A0 =A0data to be written into the
> memory, coming from the ALU.
>
> output =A0[`DATA_WIDTH-1:0] =A0 =A0 =A0 rd_data1; =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 // =A0 =A0 =A0first operand read from memory.
> output =A0[`DATA_WIDTH-1:0] =A0 =A0 =A0 rd_data2; =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 // =A0 =A0 =A0second operand read from
> memory.
>
> wire =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0clk;
> wire =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0rst;
> wire =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0we;
> wire =A0 =A0[`ADDR_LEN-1:0] =A0 =A0 =A0 =A0 rd_addr1;
> wire =A0 =A0[`ADDR_LEN-1:0] =A0 =A0 =A0 =A0 rd_addr2;
> wire =A0 =A0[`ADDR_LEN-1:0] =A0 =A0 =A0 =A0 wr_addr;
> wire =A0 =A0[`DATA_WIDTH-1:0] =A0 =A0 =A0 wr_data;
> wire =A0 =A0[`DATA_WIDTH-1:0] =A0 =A0 =A0 rd_data1;
> wire =A0 =A0[`DATA_WIDTH-1:0] =A0 =A0 =A0 rd_data2;
>
> reg =A0 =A0 [`DATA_WIDTH-1:0] =A0 =A0 =A0 ram =A0 =A0 [`RAM_DEPTH-1:0]; =
=A0 =A0 =A0 // =A0 =A0 =A0RAM memory of size
> 256X8
>
> always @ (posedge clk)
> begin
> =A0 =A0 =A0 =A0 if (rst) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0// =A0 =A0 =A0on reset, the =
following value gets stored in data
> memory.
> =A0 =A0 =A0 =A0 begin
> ram =A0 =A0 [ =A0 =A0 =A0 0 =A0 =A0 =A0 ] =A0 =A0 =A0 <=3D =A0 8'd1;
> ram =A0 =A0 [ =A0 =A0 =A0 1 =A0 =A0 =A0 ] =A0 =A0 =A0 <=3D =A0 8'd1;
> ram =A0 =A0 [ =A0 =A0 =A0 2 =A0 =A0 =A0 ] =A0 =A0 =A0 <=3D =A0 8'd1;
> // like that, it goes.
> ram =A0 =A0 [ =A0 =A0 =A0 254 =A0 =A0 ] =A0 =A0 =A0 <=3D =A0 8'd1;
> ram =A0 =A0 [ =A0 =A0 =A0 255 =A0 =A0 ] =A0 =A0 =A0 <=3D =A0 8'd1;
>
> =A0 =A0 =A0 =A0 end
>
> =A0 =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (we)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ram[wr_addr]<=3D wr_data;
> end
>
> // =A0 =A0 =A0Read operation
>
> assign =A0rd_data1=3D ram[rd_addr1]; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0// =A0 =A0 =A0first data is read from memory
> asynchronously.
> assign =A0rd_data2=3D ram[rd_addr2]; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0// =A0 =A0 =A0second data is read from memory
> asynchronously.
>
> endmodule

Your initialization process as described requires a RAM whose
data can all be reset at once.  These don't exist unless you
build it out of registers...

You can initialize the RAM at time 0 (this is different
than initializing it during "rst") using an initial block
like:

initial begin
 ram     [       0       ]       <=3D   8'd1;
 ram     [       1       ]       <=3D   8'd1;
 ram     [       2       ]       <=3D   8'd1;
 // like that, it goes.
 ram     [       254     ]       <=3D   8'd1;
 ram     [       255     ]       <=3D   8'd1;
end

Also as coded, the readout is not registered.  In most FPGA's
this precludes the use of block RAM's and puts you into
a distributed memory.  If you don't really need to have
asynchronous readout, I would suggest putting your readout
into a clocked process.

Regards,
Gabor