f



Referenced signal not in sensitivity list

Hi Folks,
I have the following where I choose not to include the signal
fifo_head_pointer in the sensitivity list since I want the block to be
evaluated only when clk , data_in or work_in change. The synthesis
tool reports the following warning

Referenced signal not in sensitivity list.  This may cause simulation
mismatches between the original and synthesized designs

Do I really have to worry about this warning? Can I just ignore it?

always @ (clk  or data_in or work_in) begin // begin always
	if(clk==1 && work_in ==1) begin
	 read=1;
	 case(fifo_head_pointer)
	  0: memory0 = data_in;
	  1: memory1 = data_in;
	  2: memory2 = data_in;
	  3: memory3 = data_in;
	  4: memory4 = data_in;
	  5: memory5 = data_in;
	  6: memory6 = data_in;
	  7: memory7 = data_in;
	  8: memory8 = data_in;
	  9: memory9 = data_in;
	  10: memory10 = data_in;
	  11: memory11 = data_in;
	  12: memory12 = data_in;
	  13: memory13 = data_in;
	  14: memory14 = data_in;
	  15: memory15 = data_in;
	 endcase//case(fifo_head_pointer)
	end // if
end  // end always

Thanks for any hint.
GA
0
nike
9/20/2008 2:22:36 PM
comp.lang.verilog 3837 articles. 2 followers. Post Follow

3 Replies
1816 Views

Similar Articles

[PageSpeed] 46

nike wrote:
> Hi Folks,
> I have the following where I choose not to include the signal
> fifo_head_pointer in the sensitivity list since I want the block to be
> evaluated only when clk , data_in or work_in change. The synthesis
> tool reports the following warning
> 
> Referenced signal not in sensitivity list.  This may cause simulation
> mismatches between the original and synthesized designs
> 
> Do I really have to worry about this warning? Can I just ignore it?
> 
> always @ (clk  or data_in or work_in) begin // begin always
> 	if(clk==1 && work_in ==1) begin
> 	 read=1;
> 	 case(fifo_head_pointer)
> 	  0: memory0 = data_in;
> 	  1: memory1 = data_in;
> 	  2: memory2 = data_in;
> 	  3: memory3 = data_in;
> 	  4: memory4 = data_in;
> 	  5: memory5 = data_in;
> 	  6: memory6 = data_in;
> 	  7: memory7 = data_in;
> 	  8: memory8 = data_in;
> 	  9: memory9 = data_in;
> 	  10: memory10 = data_in;
> 	  11: memory11 = data_in;
> 	  12: memory12 = data_in;
> 	  13: memory13 = data_in;
> 	  14: memory14 = data_in;
> 	  15: memory15 = data_in;
> 	 endcase//case(fifo_head_pointer)
> 	end // if
> end  // end always
> 
> Thanks for any hint.
> GA

You have two choices: your result ends up in registers (or a memory) 
such that you have a process that is clocked and only clocked or you 
have a combinatorial block where your result goes through several LUTs 
(and maybe some unintended latches).

Are you doing your first Verilog after years as a VHDL designer?  Are 
you new to synthesis?  Are you a first-time HDL designer?

Do you honestly want your memory entries to change whenever the data 
changes while clock and work_in are high?  This is not the normal 
operation of a memory array.

A typical function that you're trying to implement wants to clock data 
in at the rising clock edge when the work_in enables the process.  For 
that you use a clocked block with only the clock edge in the sensitivity 
list.  Changes in data will not continue to change the memory elements 
while clk and work_in happen to still be high.

Oh - and tab characters (^I) are evil.  They don't transport between 
editors well at all.

always @(posedge clk)  // just the posedge clk for clean registers
begin // begin always
   if( work_in )
   begin
     read <= 1;
     case( fifo_head_pointer )
       0: memory0 <= data_in;
       1: memory1 <= data_in;
       2: memory2 <= data_in;
       3: memory3 <= data_in;
       4: memory4 <= data_in;
       5: memory5 <= data_in;
       6: memory6 <= data_in;
       7: memory7 <= data_in;
       8: memory8 <= data_in;
       9: memory9 <= data_in;
       10: memory10 <= data_in;
       11: memory11 <= data_in;
       12: memory12 <= data_in;
       13: memory13 <= data_in;
       14: memory14 <= data_in;
       15: memory15 <= data_in;
     endcase  // case( fifo_head_pointer )
   end // if( work_in )
end  // end always

My personal belief - and you can keep the way you do things if you 
believe in it - is that commenting the begin and end lines only adds to 
clutter and makes the indentation-based formatting of the blocks less 
easy to read in the end because of the added clutter.  Personal 
preference only.

The use of non-blocking operators (<=) is typical in synthesized, 
clocked logic.  If you're not sure about the difference between blocking 
and non-blocking operators, I'd suggest doing a little reading on that 
specific subject.

If you're really trying to synthesize an array of latches and don't want 
the fifo_head_pointer to change while the clock and work_in are high, 
you'll need to register the fifo_head_pointer outside the block and 
include the registered value in your sensitivity list.  But be warned: 
latches are not the typical synthesized element and are often not 
implemented as well as the designer might want.  You certainly won't end 
up with a memory but instead an array of latches.

- John_H
0
John_H
9/20/2008 3:47:11 PM
Thanks for the extensive explanations.
The function I am implementing is a FIFO that reads data from the bus
when clk and work_in are both high. Similarly, data is written to the
bus when the head and tail pointer are not equal, there is space left
in the consumer and clk is high.
//
// write to the bus
//
always @ (clk ) begin // begin always
if(clk==1 && (fifo_head_pointer != fifo_tail_pointer) && space_left_in
==1) begin
 write=1;
 work_out=1;
 case(fifo_tail_pointer)
  0: data_out =  memory0;
  1: data_out =  memory1;
  2: data_out =  memory2;
  3: data_out =  memory3;
  4: data_out =  memory4;
  5: data_out =  memory5;
  6: data_out =  memory6;
  7: data_out =  memory7;
  8: data_out =  memory8;
  9: data_out =  memory9;
  10: data_out =  memory10;
  11: data_out =  memory11;
  12: data_out =  memory12;
  13: data_out =  memory13;
  14: data_out =  memory14;
  15: data_out =  memory15;
 endcase
 end
end

Both read and write are taken from a book (in German) by Ulrich Golze:
VLSI-Entwurf eines RISC-Prozessors (the English translation would be
VLSI design of a RISC processor).
The exact lines of the book are the following:

//read from the bus
always @(CP or DATA_IN or WORK_IN)
 if(CP==1 && WORK_IN == 1) begin
  MEMORY [HEAD]= DATA_IN;
  READ=1;
end

//write to the bus
always @(CP)
 if(CP==1 && HEAD != TAIL && SPACELEFT_IN ==1) begin
  DATA_OUT = MEMORY [TAIL] ;
 WORK_OUT=1;
 WRITE=1;
end

As the title suggests, the book presents the design of a complete RISC
processors. It also displays some pictures of the fabricated chip. I
hence assumed that the example given in the book were trustworthy.
Simulation seemed to be fine too. I started having troubles when
trying to synthesize the design.
GA


On Sep 20, 11:47 am, John_H <newsgr...@johnhandwork.com> wrote:

>
> You have two choices: your result ends up in registers (or a memory)
> such that you have a process that is clocked and only clocked or you
> have a combinatorial block where your result goes through several LUTs
> (and maybe some unintended latches).
>
> Are you doing your first Verilog after years as a VHDL designer?  Are
> you new to synthesis?  Are you a first-time HDL designer?
>
> Do you honestly want your memory entries to change whenever the data
> changes while clock and work_in are high?  This is not the normal
> operation of a memory array.
>
> A typical function that you're trying to implement wants to clock data
> in at the rising clock edge when the work_in enables the process.  For
> that you use a clocked block with only the clock edge in the sensitivity
> list.  Changes in data will not continue to change the memory elements
> while clk and work_in happen to still be high.
>
> Oh - and tab characters (^I) are evil.  They don't transport between
> editors well at all.
>
> always @(posedge clk)  // just the posedge clk for clean registers
> begin // begin always
>    if( work_in )
>    begin
>      read <= 1;
>      case( fifo_head_pointer )
>        0: memory0 <= data_in;
>        1: memory1 <= data_in;
>        2: memory2 <= data_in;
>        3: memory3 <= data_in;
>        4: memory4 <= data_in;
>        5: memory5 <= data_in;
>        6: memory6 <= data_in;
>        7: memory7 <= data_in;
>        8: memory8 <= data_in;
>        9: memory9 <= data_in;
>        10: memory10 <= data_in;
>        11: memory11 <= data_in;
>        12: memory12 <= data_in;
>        13: memory13 <= data_in;
>        14: memory14 <= data_in;
>        15: memory15 <= data_in;
>      endcase  // case( fifo_head_pointer )
>    end // if( work_in )
> end  // end always
>
> My personal belief - and you can keep the way you do things if you
> believe in it - is that commenting the begin and end lines only adds to
> clutter and makes the indentation-based formatting of the blocks less
> easy to read in the end because of the added clutter.  Personal
> preference only.
>
> The use of non-blocking operators (<=) is typical in synthesized,
> clocked logic.  If you're not sure about the difference between blocking
> and non-blocking operators, I'd suggest doing a little reading on that
> specific subject.
>
> If you're really trying to synthesize an array of latches and don't want
> the fifo_head_pointer to change while the clock and work_in are high,
> you'll need to register the fifo_head_pointer outside the block and
> include the registered value in your sensitivity list.  But be warned:
> latches are not the typical synthesized element and are often not
> implemented as well as the designer might want.  You certainly won't end
> up with a memory but instead an array of latches.
>
> - John_H

0
nike
9/21/2008 12:45:48 AM
On Sep 20, 5:45 pm, nike <gkamen...@gmail.com> wrote:
>
> As the title suggests, the book presents the design of a complete RISC
> processors. It also displays some pictures of the fabricated chip. I
> hence assumed that the example given in the book were trustworthy.
> Simulation seemed to be fine too. I started having troubles when
> trying to synthesize the design.
> GA
>

And they very well may be trustworthy examples.  You're using a
different synthesizer, and are discovering the various ways of
creating simulation/synthesizer miss-matches.  Which is a very
valuable thing to learn.
0
LittleAlex
9/24/2008 3:39:28 PM
Reply:

Similar Artilces:

List of lists of lists of lists...
I would like to have a list of lists N times deep, and my solution is (in pseudocode): def deep(x): a=[x] return a mylist=[] for N: mylist=deep(mylist) Is there a more elegant way to do it? The maine idea is: from a list having the numbre of steps along N dimensions, generate a list with an item at each possible point. Example 1: N=2 list=[2,3] result=[[1,2],[1,2],[1,2]] Example 2: N=3 list=[3,1,2] result=[[[1,2,3]],[[1,2,3]]] -- Ángel Gutiérrez Rodríguez - agr@fq.uniovi.es Instituto de Ciencia de los Materiales de Madrid - CSIC SpLine - European Syncrothorn Radiat...

redundant signals in sensitivity list?
Hello, I have come across the following VHDL example describing a D flip-flop with preset and clear. It seems to me that clr and pr can be omitted entirely from the process's sensitivity list as the only time one of these will change is when clr_l or pr_l will change. Is this so or do the signals clr and pr (clear and preset) really have to be included in the sensitivity list as well? Thanks, Neil library ieee; use ieee.std_logic_1164.all; entity ff is port (d, clk, pr_l, clr_l: in std_logic; q, qn: out std_logic); end entity ff; architecture arch of ff is signal pr, cl...

std_logic_vector signals in sensitivity list process
Hello all, I have some questions about how to use std_logic_vector signals in the sensitivity list of a process. First of all, is the sensitivity list like a comparator in hardware and does it continuously checks if the value changes? Or is the sensitivity list only important when simulating the design? If I use a std_logic_vector signal in the sensitivity list, are all the bits of this signal compared or is only one bit(MSB of LSB) used? Is there a difference between those two sensitivity lists? process(port_a(4 downto 0)) begin -- do something end process process(port_a(3), port_a(2),...

list of lists of lists ....
Hi, I have a list of data (type A) my list can includes element of type A or a lists, these list can includes element of type A or a lists, and so on ... is there a simple way to obtain a single list of all the elemets of type A ? thanks yomgui I forgot the most important, I am looking for a non recursive method. thanks yomgui yomgui wrote: > > Hi, > > I have a list of data (type A) > my list can includes element of type A or a lists, > these list can includes element of type A or a lists, and so on ... > > is there a simple way to obtain a single list of all the elemets > of type A ? > > thanks > > yomgui recursion. def get_As(L): res = [] for elem in L: if isinstance(elem, A): res.append(elem) elif isinstance(elem, list): res += get_As(elem) return res i also have a Tree class in my rc: http://home.comcast.net/~faulkner612/programming/python/pythonrc.py yomgui wrote: > Hi, > > I have a list of data (type A) > my list can includes element of type A or a lists, > these list can includes element of type A or a lists, and so on ... > > is there a simple way to obtain a single list of all the elemets > of type A ? > > thanks > > yomgui doh. ok, so, recursion is just functional programming sugar for a loop. def get_As(L): checking = [elem for elem in L if isinstance(elem, list)] # the equivalent of elem in recursion all_As =...

multi-bit signal in sensitivity list with partial use
HI, We have a 8 bit signal in1[7:0]. We are using only 2 LSB bits in side a combinatorial always process. Is it ok to use the complete bus in the sensitivity list? Can there be any problem during simulation? We are not able to come up with an error case. If anyone out there has experience with this, we would like to hear from them. For example, wire [7:0] in1; .... ... always @ ( in1, ..<other signals>...) begin out1 = in1[1:0] + <other signals>; end vs always @ ( in1[1:0], ..<other signals>...) begin out1 = in1[1:0] + <other signals>; end The add function is just an example. We have a complex MUX logic here which makes it impractical to with a "?:" procedural statement. Thanks. -Dipu > We have a 8 bit signal in1[7:0]. We are using only 2 LSB bits in side > a combinatorial always process. Is it ok to use the complete bus in > the sensitivity list? It depends. For sythesizable stuff, you should be fine, although DC will probably give you a warning. However, you can never win because other tools will give you a warning if you don't use the full signal. > Can there be any problem during simulation? We > are not able to come up with an error case. Here's an example, but this is just muppet coding: always @(in1) $display(in[1:0]); always @(in1[1:0]) $display(in[1:0]); Depending on which code is used, $display could be called a differe...

One or more signals are missing in the sensitivity list of always block.
Hi experts. I'm really new to Verilog and digital circuit.(and english) I'm studying Verilog now and trying to design a module that will receive data in LVDS. the following is my code. When I synthesised this, I received the following Warning message. ************************************************************************ WARNING:Xst:905 - "LVDS_Rcv.v" line 46: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note...

Sort a List, in a List of Lists of Lists
Dear Mathgroup, I have a lsit of Lists of Lists: {{{1,2},{2,1},{1,1}},{{1,1},{1,1},{1,2}},{{2,1},{2,2},{1,2}},{{2,2},{1,2},{2,2}},{{1,1},{2,1},{1,2}},{{1,2},{2,2},{2,2}}} I would like to sort the elements in the lowest level of brackets to give {{{1, 2}, {1, 2}, {1, 1}}, {{1, 1}, {1, 1}, {1, 2}}, {{1, 2}, {2, 2}, {1, 2}}, {{2, 2}, {1, 2}, {2, 2}}, {{1, 1}, {1, 2}, {1, 2}}, {{1, 2}, {2, 2}, {2, 2}}} i.e retaining the same structure with the paired elements in the original order. I can't seem to get the syntax right to do this apart from the obvious {{Sort[{1,...

Re: Sort a List, in a List of Lists of Lists
On 11/13/10 at 12:59 AM, leigh.pascoe@inserm.fr wrote: >I have a lsit of Lists of Lists: >{{{1,2},{2,1},{1,1}},{{1,1},{1,1},{1,2}},{{2,1},{2,2},{1,2}},{{2,2}, >{1,2},{2,2}},{{1,1},{2,1},{1,2}},{{1,2},{2, 2},{2,2}}} >I would like to sort the elements in the lowest level of brackets to >give >{{{1, 2}, {1, 2}, {1, 1}}, {{1, 1}, {1, 1}, {1, 2}}, {{1, 2}, {2, >2}, {1, 2}}, {{2, 2}, {1, 2}, {2, 2}}, {{1, 1}, {1, 2}, {1, 2}}, >{{1, 2}, {2, 2}, {2, 2}}} >i.e retaining the same structure with the paired elements in the >original order. I can't seem...

Extracting a List from a List of lists
Hi, I have an ArrayList of ArrayLists. I want to extract all the lists, but I dont know how many ArrayLists will be in the ArrayList. I know I can do it if i know how many lists are there using the ArrayList get() method. this is how i'm doing it List<String> list1 = new ArrayList<String>(); list1 = res.get(0); List<String> list1 = new ArrayList<String>(); list2 = res.get(1); List<String> list1 = new ArrayList<String>(); list3 = res.get(2); But if theres only two lists in the list i get a NullPointerException Is there any way i can loop through the l...

Copying a List to a List of Lists
Hi, I am having trouble with the following: I wish to have a list of lists of type Double called A. I then have a separate List of Doubles called B which i wish to add to A. I then want to be able to clear B and reuse it without clearing what I have added to A. Currently my code looks like: for(int i=0;i<seqLength;i++) { B.clear(); for(int j=i+1;j<seqLength;j++) { if(fourGameteTest(i,j)) { B.add(segPositions.get(j)); } } A.get(i).add(B); } However, it seems that due to, I guess the element held in A being a reference to the same place as B, when B is cleared A ends up having no elements. How can I do this so as to be able to reuse B but not lose what I have stored in A? Thanks, Alex This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig13D766A4299F198A3B856CA7 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Alex schreef: > Hi, >=20 > I am having trouble with the following: I wish to have a list of lists > of type Double called A. I then have a separate List of Doubles called > B which i wish to add to A. I then want to be able to clear B and reuse= > it without clearing what I have added to A. >=20 > Currently my code looks like: >=20 > for(int i=3D0;i<seqLength;i++) > { > B.clear(); >=20 > for(int j=3Di+1;j<seqLength;j++) > { > if(fourGameteTest(i,j)) > { > B.add(seg...

List of Atom or List of List??
how can detect some element of list is list o Atom?? for example when i try head (head p1) where p1=[[1,2],2] return 1 but when try head (head p1) where p1=[1,2] it returns Error plz help me..it my project and i have just 2 hours..:( i want to replace on Atom by another in list..for example: replace 1 2 [1,2] => [2,2] but sometime i have replace 1 2 [[1,2],2]=>[[2,2],2] i want to detect if first element of list is list then recurcively call head on that element.. is there any solutions?? On 8 Apr 2007 02:46:25 -0700, kheirandish.amin@gmail.com wrote: >how can detect some element of list is list o Atom?? (list? 42) --> #f (list? '(42 37)) --> #t Steve Schafer Fenestra Technologies Corp. http://www.fenestra.com/ in Haskell plz, not Scheme In article <1176025585.229021.233310@w1g2000hsg.googlegroups.com>, <kheirandish.amin@gmail.com> wrote: > how can detect some element of list is list o Atom?? What is an atom? That is term is not commonly used with Haskell. > for example > when i try head (head p1) where p1=[[1,2],2] return 1 > but when try head (head p1) where p1=[1,2] it returns Error It doesn't _return_ an error, but your expression fails to type-check. Haskell's lists are homogeneous, i.e. all the elements are of the same type. So either _all_ elements are lists (in which case the list of lists has type [[a]] for some type a), or none of them are (in which case the list has type [b] for some type ...

How to have a list of lists (or array of lists)
Hi, I want to have many lists, such as list0, list1, list2, ..., each one holding different number of items. Is there something like list[0] list[1] list[2] so that I can iterate through this list of lists? Thanks! bahoo On Apr 3, 7:12 pm, "bahoo" <b83503...@yahoo.com> wrote: > Hi, > > I want to have many lists, such as list0, list1, list2, ..., each one > holding different number of items. > Is there something like > list[0] > list[1] > list[2] > > so that I can iterate through this list of lists? > > Thanks! > bahoo listOfLists = [...

convert list of lists to list
Is there a way to convert list_of_listsA to list_of_listsB, where one list in listof lists A is one element of listB? list_of_listsA: [['klas*', '*', '*'], ['mooi*', '*', '*', '*'], ['koe'], ['arm*', '*', '*(haar)'], ['groei*', '*', '*', '*', '*']] listB: ['klas* * *', 'mooi* * * *, 'koe', 'arm* * * (haar)', 'groei* * * * *'] Thankx! antar2 wrote: > Is there a way to convert list_of_listsA to list_of_listsB, where one >...

lists of lists
I'm using C++ and I'm trying to create a list of a list and it won't let me create an iterator for it. if I do a list of an int, everything is fine. my syntax is list<list<string> > some_list; and my iterator would be someting like list<list>::Iterator blah; or maybe list<list<string> >::Iterator blah; ?? neither work, ofcourse. basicaly I'm trying to parse a text file, each line is token that contains tokens and I have a function that takes a string and returns the list of the tokens. so I have my the parent list to contain lists to t...

List referencing
I've been slowing creating some commands (with help from many of the folks here!) to help me create a test that will show/hide answers based on a boolean switch. OK, all that works just fine. The problem comes about when I want to label and reference any of the answers. Here's a minimal example that will illustrate the problem: === \documentclass{article} \usepackage{ifthen} \newboolean{showanswers} \setboolean{showanswers}{true} %\setboolean{showanswers}{false} %%% Change the counter labels \renewcommand{\labelenumi}{\arabic{enumi}.} \renewcommand{\labelenumii}{\alph{enumii}.} %...

List of lists...
I would like to add a List environment with an accompanying list of lists included at the front of the document. Basically, a List is like a table or a figure. However, I want to be able to refer to a bulleted list. I am using gatech-thesis.cls (which is based on report.cls). I went through report.cls, and copied everything having to do with figures into gatech-thesis.cls (just after it includes report.cls) and changed everything that said figure to list. Then, I went through gatech-thesis.cls, and copied everything having to do with figures, changing everything that said figure to list.....

List of a list
Hi, I'm very new to latex. I'm trying to make a list of a list, with: \begin{list}{} \item \begin{list}{} \item \end{list} \end{list} However, I'm getting the error: Runaway argument? ! Paragraph ended before \list was complete. <to be read again> \par l.2273 However, I can do a list of enumerates, but that's not what I want. Is this a clash in syntax? Is there a way to prevent this? Please help. Michael On 1 Nov 2004 00:19:43 -0800, Michael <dayzman@hotmail.com> wrote: > Hi, > I'm very new to latex. I'm trying to make a list ...

list or not a list?
Hello, I was a bit astonished using such tcl code: % set list "Abbruch der Aktion \" ##ACTION \" !" Abbruch der Aktion " ##ACTION " ! % llength $list 5 % llength [split $list] 7 % % set idx 0 0 % foreach element $list {puts "element($idx) = '$element'"; incr idx} element(0) = 'Abbruch' element(1) = 'der' element(2) = 'Aktion' element(3) = ' ##ACTION ' element(4) = '!' % % set idx 0 0 % foreach element [split $list] {puts "ele...

Lists of list
Hi All I am having problem with delete line if its belong to another one , example ['0132442\n', '13\n', '24\n'] the 2nd and 3rd are already in the first line , how can do this !!! Thanks Mohammed Altaj wrote: > Hi All > > I am having problem with delete line if its belong to another one , example I think, you mean to remove all lines that are substrings of another line. l = ['0132442\n', '13\n', '24\n'] l = [e.strip() for e in l] i = 0 while True: try: for j in range(len(l)): if i == j: continue if l[j]...

Lists from Lists
Can anyone tell me how can I make a list from all the first elements of the following pairs? l:=[[1,2],[3,4],[5,6],[7,8]] ; to get, m:=[1,3,5,7]; Thanks, Tony Connell "Tony Connell" <a.connell@galileo.karoo.co.uk> wrote in message news:vfk59prj7bp0fb@corp.supernews.com... > Can anyone tell me how can I make a list from all the first elements of the > following pairs? > > l:=[[1,2],[3,4],[5,6],[7,8]] ; > > to get, > > m:=[1,3,5,7]; > If you know the length of the list you could do like this: > m:=[seq(l[i][1], i=1..4)]; -Reidar Kind Tony Connell" <a.connell@galileo.karoo.co.uk> wrote: > Can anyone tell me how can I make a list from all the first elements of > the following pairs? > l:=[[1,2],[3,4],[5,6],[7,8]] ; map2(op, 1, l); "Tony Connell" <a.connell@galileo.karoo.co.uk> wrote in message news:vfk59prj7bp0fb@corp.supernews.com... > Can anyone tell me how can I make a list from all the first elements of the > following pairs? > > l:=[[1,2],[3,4],[5,6],[7,8]] ; > > to get, > > m:=[1,3,5,7]; m:=l[1..-1,1]; Alec Mihailovs http://webpages.shepherd.edu/amihailo/ "Reidar Kind" <s989788@stud.nhh.no> wrote in message news:A%oKa.13616$KF1.276672@amstwist00... > > "Tony Connell" <a.connell@galileo.karoo.co.uk> wrote in message > news:vfk59prj7bp0fb@cor...

When is a List not a List?
g[x_, n_] := x^n FullForm[Table[g[x, n], {n, 1, 2}]] FullForm[{g[x, 1], g[x, 2]}] Plot[{g[x, 1], g[x, 2]}, {x, 0, 1}, PlotStyle -> {Red, Blue}] Plot[Table[g[x, n], {n, 1, 2}], {x, 0, 1}, PlotStyle -> {Red, Blue}] The FullForm[]s are identical. One Plot[] has red and blue curves; the other has two blue curves. Quirky! AES wrote: > g[x_, n_] := x^n > FullForm[Table[g[x, n], {n, 1, 2}]] > FullForm[{g[x, 1], g[x, 2]}] > Plot[{g[x, 1], g[x, 2]}, {x, 0, 1}, PlotStyle -> {Red, Blue}] > Plot[Table[g[x, n], {n, 1, 2}], {x, 0, 1}, PlotStyle -> {Red, Blue}] > > The FullForm[]s are identical. One Plot[] has red and blue curves; the > other has two blue curves. > > Quirky! Not at all, as it has already been explained many times in this very newsgroup (notwithstanding the online help that contains some examples illustrating this point). Plot does not evaluate immediately its arguments because it has the attribute HoldAll: Attributes[Plot] {HoldAll, Protected} So, having the attribute HoldHold, what Plot "sees" in first instance the unevaluated expression Table[g[x, n], {n, 1, 2}], which stands for only *one* function. Thus the choice of colors is just for one function/expression, not for the list of functions that will be returned after evaluation of the first argument. To force the evaluation of the first argument before doing anythin...

sensitivity list
Can you have two process in an architecture sensitive to the same signal? (e.g. clock). Thanks. Eqbal wrote: > Can you have two process in an architecture sensitive to the same > signal? (e.g. clock). Yes. As many as you want. You can even add "reset" to the lists. -- Mike Treseler Eqbal wrote: > Can you have two process in an architecture sensitive to the same > signal? (e.g. clock). > > Thanks. yes you can. a lot of processes can be sensitive to the same signal. -- Dietl Herwig I am Murphy of Borg: Anything that can be assimilated will be. ...

List of lists
So you can create listoffigures tableofcontents and listoftables, but can you and if so how do you do the same thing for a list of numbered lists? Cheers Try the tocloft package: http://www.ctan.org/tex-archive/help/Catalogue/entries/tocloft.html On 21 Mar, 17:26, "Matt" <matthew.w.tur...@gmail.com> wrote: > Try the tocloft package: > > http://www.ctan.org/tex-archive/help/Catalogue/entries/tocloft.html That looks great, cheers. But I am having trouble using it. This is the code I am trying, just lifted from the instructions: \newcommand{\listanswername}{List o...

Sensitivity List
Hi everybody, I would like to ask about the way you declare the sensitivity list in an always block.I tried to use the always@(*) statement but Modelsim seems that it doesn't accept it,eventhough this statement is accepted in Synpllicity's Synplify synthesis tool. Do i have to declare every signal separately?Also,i have a module with a register file (an array of 20 8-bit registers),and although the synthesis tool shows a warning if the register file misses from the sensitivity list,Modelsim gives an error when i include it in the sensitivity list.Any help?? Thanks in advance, Yiannis yiannis wrote: .... > Also,i have a module with a register file (an array > of 20 8-bit registers),and although the synthesis tool shows a warning > if the register file misses from the sensitivity list,Modelsim gives an > error when i include it in the sensitivity list.Any help?? A synchronous block needs only reset and clock in the list and will be accepted by both tools without warnings. -- Mike Treseler It's not a synchronous block.it's about an fsm where i have two separate blocks,one combinational and one sequential.What i described before was about the combinational logic block. yiannis wrote: > It's not a synchronous block.it's about an fsm where i have two > separate blocks,one combinational and one sequential.What i described > before was about the combinational logic block. I would combine...

Web resources about - Referenced signal not in sensitivity list - comp.lang.verilog

Sensitivity and specificity - Wikipedia, the free encyclopedia
Sensitivity and specificity are statistical measures of the performance of a binary classification test , also known in statistics as classification ...

Google Case Sensitivity - Flickr - Photo Sharing!
More at searchengineland.com/080620-081736.php

El wire touch sensitivity experiment - YouTube
Hi, this is a demonstration of the effect I discovered of "angel hair" EL wire being touch sensitive when pressed in some orientations. Also ...

James Williams: British barber’s sensitivity towards autistic boy praised - AdelaideNow Search Search ...
HAIRDRESSERS are no strangers to tough clients but a British barber is being praised for doing the hard yards to give a toddler with autism his ...

Researchers Who Provided Key Evidence For Gluten Sensitivity Have Thoroughly Shown That It Doesn't Exist ...
In one of the best examples of science working, a researcher who provided key evidence of (non-celiac disease) gluten sensitivity recently published ...

Panasonic doubles color sensitivity of digital camera sensors
Panasonic has developed a new way to drastically increase the color and light sensitivity of digital cameras including those used in smartphones. ...

James Williams: British barber’s sensitivity towards autistic boy praised - The Courier-Mail Search Search ...
HAIRDRESSERS are no strangers to tough clients but a British barber is being praised for doing the hard yards to give a toddler with autism his ...

James Williams: British barber’s sensitivity towards autistic boy praised
HAIRDRESSERS are no strangers to tough clients but a British barber is being praised for doing the hard yards to give a toddler with autism his ...

Hajj pilgrims promised sensitivity
... for joining an illegal war will be targeted, the government says. Pilgrims travelling to Saudi Arabia for the Hajj will be treated with sensitivity ...

Global satellite map highlights sensitivity of Australia's plants to changes in rainfall and temperature ...
Australia's outback plants may have given up, according to maps tracking the impact of changing climatic conditions on ecosystems.

Resources last updated: 3/10/2016 10:33:03 AM