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#### Referenced signal not in sensitivity list

Hi Folks,
I have the following where I choose not to include the signal
fifo_head_pointer in the sensitivity list since I want the block to be
evaluated only when clk , data_in or work_in change. The synthesis
tool reports the following warning

Referenced signal not in sensitivity list.  This may cause simulation
mismatches between the original and synthesized designs

Do I really have to worry about this warning? Can I just ignore it?

always @ (clk  or data_in or work_in) begin // begin always
if(clk==1 && work_in ==1) begin
0: memory0 = data_in;
1: memory1 = data_in;
2: memory2 = data_in;
3: memory3 = data_in;
4: memory4 = data_in;
5: memory5 = data_in;
6: memory6 = data_in;
7: memory7 = data_in;
8: memory8 = data_in;
9: memory9 = data_in;
10: memory10 = data_in;
11: memory11 = data_in;
12: memory12 = data_in;
13: memory13 = data_in;
14: memory14 = data_in;
15: memory15 = data_in;
end // if
end  // end always

Thanks for any hint.
GA

 0
nike
9/20/2008 2:22:36 PM
comp.lang.verilog 3837 articles. 2 followers.

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nike wrote:
> Hi Folks,
> I have the following where I choose not to include the signal
> fifo_head_pointer in the sensitivity list since I want the block to be
> evaluated only when clk , data_in or work_in change. The synthesis
> tool reports the following warning
>
> Referenced signal not in sensitivity list.  This may cause simulation
> mismatches between the original and synthesized designs
>
> Do I really have to worry about this warning? Can I just ignore it?
>
> always @ (clk  or data_in or work_in) begin // begin always
> 	if(clk==1 && work_in ==1) begin
> 	  0: memory0 = data_in;
> 	  1: memory1 = data_in;
> 	  2: memory2 = data_in;
> 	  3: memory3 = data_in;
> 	  4: memory4 = data_in;
> 	  5: memory5 = data_in;
> 	  6: memory6 = data_in;
> 	  7: memory7 = data_in;
> 	  8: memory8 = data_in;
> 	  9: memory9 = data_in;
> 	  10: memory10 = data_in;
> 	  11: memory11 = data_in;
> 	  12: memory12 = data_in;
> 	  13: memory13 = data_in;
> 	  14: memory14 = data_in;
> 	  15: memory15 = data_in;
> 	end // if
> end  // end always
>
> Thanks for any hint.
> GA

You have two choices: your result ends up in registers (or a memory)
such that you have a process that is clocked and only clocked or you
have a combinatorial block where your result goes through several LUTs
(and maybe some unintended latches).

Are you doing your first Verilog after years as a VHDL designer?  Are
you new to synthesis?  Are you a first-time HDL designer?

Do you honestly want your memory entries to change whenever the data
changes while clock and work_in are high?  This is not the normal
operation of a memory array.

A typical function that you're trying to implement wants to clock data
in at the rising clock edge when the work_in enables the process.  For
that you use a clocked block with only the clock edge in the sensitivity
list.  Changes in data will not continue to change the memory elements
while clk and work_in happen to still be high.

Oh - and tab characters (^I) are evil.  They don't transport between
editors well at all.

always @(posedge clk)  // just the posedge clk for clean registers
begin // begin always
if( work_in )
begin
0: memory0 <= data_in;
1: memory1 <= data_in;
2: memory2 <= data_in;
3: memory3 <= data_in;
4: memory4 <= data_in;
5: memory5 <= data_in;
6: memory6 <= data_in;
7: memory7 <= data_in;
8: memory8 <= data_in;
9: memory9 <= data_in;
10: memory10 <= data_in;
11: memory11 <= data_in;
12: memory12 <= data_in;
13: memory13 <= data_in;
14: memory14 <= data_in;
15: memory15 <= data_in;
endcase  // case( fifo_head_pointer )
end // if( work_in )
end  // end always

My personal belief - and you can keep the way you do things if you
believe in it - is that commenting the begin and end lines only adds to
clutter and makes the indentation-based formatting of the blocks less
easy to read in the end because of the added clutter.  Personal
preference only.

The use of non-blocking operators (<=) is typical in synthesized,
clocked logic.  If you're not sure about the difference between blocking
and non-blocking operators, I'd suggest doing a little reading on that
specific subject.

If you're really trying to synthesize an array of latches and don't want
the fifo_head_pointer to change while the clock and work_in are high,
you'll need to register the fifo_head_pointer outside the block and
include the registered value in your sensitivity list.  But be warned:
latches are not the typical synthesized element and are often not
implemented as well as the designer might want.  You certainly won't end
up with a memory but instead an array of latches.

- John_H

 0
John_H
9/20/2008 3:47:11 PM
Thanks for the extensive explanations.
The function I am implementing is a FIFO that reads data from the bus
when clk and work_in are both high. Similarly, data is written to the
bus when the head and tail pointer are not equal, there is space left
in the consumer and clk is high.
//
// write to the bus
//
always @ (clk ) begin // begin always
if(clk==1 && (fifo_head_pointer != fifo_tail_pointer) && space_left_in
==1) begin
write=1;
work_out=1;
case(fifo_tail_pointer)
0: data_out =  memory0;
1: data_out =  memory1;
2: data_out =  memory2;
3: data_out =  memory3;
4: data_out =  memory4;
5: data_out =  memory5;
6: data_out =  memory6;
7: data_out =  memory7;
8: data_out =  memory8;
9: data_out =  memory9;
10: data_out =  memory10;
11: data_out =  memory11;
12: data_out =  memory12;
13: data_out =  memory13;
14: data_out =  memory14;
15: data_out =  memory15;
endcase
end
end

Both read and write are taken from a book (in German) by Ulrich Golze:
VLSI-Entwurf eines RISC-Prozessors (the English translation would be
VLSI design of a RISC processor).
The exact lines of the book are the following:

//read from the bus
always @(CP or DATA_IN or WORK_IN)
if(CP==1 && WORK_IN == 1) begin
end

//write to the bus
always @(CP)
if(CP==1 && HEAD != TAIL && SPACELEFT_IN ==1) begin
DATA_OUT = MEMORY [TAIL] ;
WORK_OUT=1;
WRITE=1;
end

As the title suggests, the book presents the design of a complete RISC
processors. It also displays some pictures of the fabricated chip. I
hence assumed that the example given in the book were trustworthy.
Simulation seemed to be fine too. I started having troubles when
trying to synthesize the design.
GA

On Sep 20, 11:47 am, John_H <newsgr...@johnhandwork.com> wrote:

>
> You have two choices: your result ends up in registers (or a memory)
> such that you have a process that is clocked and only clocked or you
> have a combinatorial block where your result goes through several LUTs
> (and maybe some unintended latches).
>
> Are you doing your first Verilog after years as a VHDL designer?  Are
> you new to synthesis?  Are you a first-time HDL designer?
>
> Do you honestly want your memory entries to change whenever the data
> changes while clock and work_in are high?  This is not the normal
> operation of a memory array.
>
> A typical function that you're trying to implement wants to clock data
> in at the rising clock edge when the work_in enables the process.  For
> that you use a clocked block with only the clock edge in the sensitivity
> list.  Changes in data will not continue to change the memory elements
> while clk and work_in happen to still be high.
>
> Oh - and tab characters (^I) are evil.  They don't transport between
> editors well at all.
>
> always @(posedge clk)  // just the posedge clk for clean registers
> begin // begin always
>    if( work_in )
>    begin
>      read <= 1;
>      case( fifo_head_pointer )
>        0: memory0 <= data_in;
>        1: memory1 <= data_in;
>        2: memory2 <= data_in;
>        3: memory3 <= data_in;
>        4: memory4 <= data_in;
>        5: memory5 <= data_in;
>        6: memory6 <= data_in;
>        7: memory7 <= data_in;
>        8: memory8 <= data_in;
>        9: memory9 <= data_in;
>        10: memory10 <= data_in;
>        11: memory11 <= data_in;
>        12: memory12 <= data_in;
>        13: memory13 <= data_in;
>        14: memory14 <= data_in;
>        15: memory15 <= data_in;
>      endcase  // case( fifo_head_pointer )
>    end // if( work_in )
> end  // end always
>
> My personal belief - and you can keep the way you do things if you
> believe in it - is that commenting the begin and end lines only adds to
> clutter and makes the indentation-based formatting of the blocks less
> easy to read in the end because of the added clutter.  Personal
> preference only.
>
> The use of non-blocking operators (<=) is typical in synthesized,
> clocked logic.  If you're not sure about the difference between blocking
> and non-blocking operators, I'd suggest doing a little reading on that
> specific subject.
>
> If you're really trying to synthesize an array of latches and don't want
> the fifo_head_pointer to change while the clock and work_in are high,
> you'll need to register the fifo_head_pointer outside the block and
> include the registered value in your sensitivity list.  But be warned:
> latches are not the typical synthesized element and are often not
> implemented as well as the designer might want.  You certainly won't end
> up with a memory but instead an array of latches.
>
> - John_H


 0
nike
9/21/2008 12:45:48 AM
On Sep 20, 5:45 pm, nike <gkamen...@gmail.com> wrote:
>
> As the title suggests, the book presents the design of a complete RISC
> processors. It also displays some pictures of the fabricated chip. I
> hence assumed that the example given in the book were trustworthy.
> Simulation seemed to be fine too. I started having troubles when
> trying to synthesize the design.
> GA
>

And they very well may be trustworthy examples.  You're using a
different synthesizer, and are discovering the various ways of
creating simulation/synthesizer miss-matches.  Which is a very
valuable thing to learn.

 0
LittleAlex
9/24/2008 3:39:28 PM

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