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SDF Error: IOPATH annotation

I am trying to do timing simulation using SDF file using vcs
simulation. These are the steps I followed

- Add to testbecnh the following construct

initial $sdf_annotate("test.sdf", test
,"sdf.cfg","test_sdf.log","MAXIMUM",);
//hierarchy in testbench file is as follows
module testbench
initial $sdf_annotate("test.sdf", test
,"sdf.cfg","test_sdf.log","MAXIMUM",);

temp test (
   ....
   ....
   ....
)

- Compile the design with following options
  vcs ... +compsdf +maxdelays 

  (I have tried with other options like +transport_path_delays
+delay_mode_distributed +pulse_on_detect and all other related
options)


- SDF file generated has both INTERCONNECT and IOPATH delays but
simulator seems to only see interconnect delays and is complaining
about IOPATH annotation. Here is the error message

********************************************************
SDF Error: IOPATH annotation not enabled for module inx2
SDF Error: IOPATH annotation not enabled for module inx2
********************************************************
This error message occurs for each and every instance of the design.


Some other details 
------------------
- SDF is generated using PrimeTime version 2003.12
- vcs version is vcs-7.1.1R8

Did anyone encounter this error? Is there any helpful documentation
online I could look into regarding SDF files and timing simulations?
0
vazzupp
6/18/2004 4:27:32 PM
comp.lang.verilog 3837 articles. 2 followers. Post Follow

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