f

#### shift arithmetic

```hello every one
in modelsim 10.0c i wrote >>>
i mean shift arithmetic but the modelsim doesn't know.
the second and third > are blue but the first > is black
help me how can write shift arithmetic in modelsim.
thanks
```
 0
a
3/13/2014 4:09:51 AM
comp.lang.verilog 3837 articles. 2 followers.

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```Hi A.H.E.J.

> i mean shift arithmetic but the modelsim doesn't know.

It is not a tool matter but a language matter.

Can you send me a description of the entire problem?

Please note that >>> denotes right rotation in some offshoot C-like languag=
es. In Verilog there are 2 or 3 usual ways of coding a left or right rotati=
on.

Best regards

Not in =CE=A4=CE=B7 =CE=A0=CE=AD=CE=BC=CF=80=CF=84=CE=B7, 13 =CE=9C=CE=B1=
=CF=81=CF=84=CE=AF=CE=BF=CF=85 2014 6:09:51 =CF=80.=CE=BC. UTC+2, =CE=BF =
=CF=88=CE=B5:
> hello every one=20
>=20
> in modelsim 10.0c i wrote >>>=20
>=20
> i mean shift arithmetic but the modelsim doesn't know.
>=20
> the second and third > are blue but the first > is black
>=20
> help me how can write shift arithmetic in modelsim.
>=20
> thanks
```
 0
Nikolaos
3/13/2014 11:22:59 AM
```thanks Nikolaos Kavvadias
my code is:
module my(b,o0,o1);
input [4:0] b;
output [4:0] o0,o1;
wire [4:0] o0;
assign b=5'b10110;//-10
assign a=0;
assign o0=(b >>> 2);//line7: shift arithmetic
assign o1=(b >> 2); //line8: shift
endmodule

but o1=o0 i don' so >>> and >> is the same?
```
 0
a
3/13/2014 12:12:26 PM
```"a.h e.j" a �crit :
> my code is:
> module my(b,o0,o1);
> input [4:0] b;
> output [4:0] o0,o1;
> wire [4:0] o0;
> assign b=5'b10110;//-10
> assign a=0;
> assign o0=(b >>> 2);//line7: shift arithmetic
> assign o1=(b >> 2); //line8: shift
> endmodule
>
> but o1=o0 i don' so >>> and >> is the same?

No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and
<<< are available in Verilog-2001 so make sure you compile in Verilog-2001
(refer to the manual of your simulator).
```
 0
Vince
3/13/2014 12:56:26 PM
```Vince wrote:
> "a.h e.j" a �crit :
>> my code is:
>> module my(b,o0,o1);
>> input [4:0] b;
>> output [4:0] o0,o1;
>> wire [4:0] o0;
>> assign b=5'b10110;//-10
>> assign a=0;
>> assign o0=(b >>> 2);//line7: shift arithmetic
>> assign o1=(b >> 2); //line8: shift
>> endmodule
>>
>> but o1=o0 i don' so >>> and >> is the same?
>
> No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and
> <<< are available in Verilog-2001 so make sure you compile in Verilog-2001
> (refer to the manual of your simulator).

I wasn't aware that Modelsim didn't support this basic feature of
Verilog 2001 unless you have a very old version.  However it was
my understanding that >>> would only operate correctly (i.e. replicate
the MSB) if the argument to be shifted was signed.

--
Gabor
```
 0
GaborSzakacs
3/13/2014 5:50:05 PM
```Hi AHEJ

what are you trying to solve/achieve? I can see an attempt to the solution =
but not a statement of the problem.

Best regards

PS: Your code syntactically passes through Icarus Verilog (which supports V=
erilog-2001).

> "a.h e.j" a =E9crit :=20
>=20
>=20
> > my code is:
>=20
> > module my(b,o0,o1);
>=20
> > input [4:0] b;
>=20
> > output [4:0] o0,o1;
>=20
> > wire [4:0] o0;
>=20
> > assign b=3D5'b10110;//-10
>=20
> > assign a=3D0;
>=20
> > assign o0=3D(b >>> 2);//line7: shift arithmetic
>=20
> > assign o1=3D(b >> 2); //line8: shift
>=20
> > endmodule
>=20
> >=20
>=20
> > but o1=3Do0 i don' so >>> and >> is the same?
>=20
>=20
>=20
> No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>>=
and
>=20
> <<< are available in Verilog-2001 so make sure you compile in Verilog-200=
1
>=20
> (refer to the manual of your simulator).
```
 0
Nikolaos
3/13/2014 8:11:20 PM

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