hello every one in modelsim 10.0c i wrote >>> i mean shift arithmetic but the modelsim doesn't know. the second and third > are blue but the first > is black help me how can write shift arithmetic in modelsim. thanks

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3/13/2014 4:09:51 AM

Hi A.H.E.J. > i mean shift arithmetic but the modelsim doesn't know. It is not a tool matter but a language matter. I can help you but holistically not specifically. Can you send me a description of the entire problem? Please note that >>> denotes right rotation in some offshoot C-like languag= es. In Verilog there are 2 or 3 usual ways of coding a left or right rotati= on. Best regards Nikolaos Kavvadias Not in =CE=A4=CE=B7 =CE=A0=CE=AD=CE=BC=CF=80=CF=84=CE=B7, 13 =CE=9C=CE=B1= =CF=81=CF=84=CE=AF=CE=BF=CF=85 2014 6:09:51 =CF=80.=CE=BC. UTC+2, =CE=BF = =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 a.h e.j =CE=AD=CE=B3=CF=81=CE=B1= =CF=88=CE=B5: > hello every one=20 >=20 > in modelsim 10.0c i wrote >>>=20 >=20 > i mean shift arithmetic but the modelsim doesn't know. >=20 > the second and third > are blue but the first > is black >=20 > help me how can write shift arithmetic in modelsim. >=20 > thanks

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3/13/2014 11:22:59 AM

thanks Nikolaos Kavvadias my code is: module my(b,o0,o1); input [4:0] b; output [4:0] o0,o1; wire [4:0] o0; assign b=5'b10110;//-10 assign a=0; assign o0=(b >>> 2);//line7: shift arithmetic assign o1=(b >> 2); //line8: shift endmodule but o1=o0 i don' so >>> and >> is the same?

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3/13/2014 12:12:26 PM

"a.h e.j" a �crit : > thanks Nikolaos Kavvadias > my code is: > module my(b,o0,o1); > input [4:0] b; > output [4:0] o0,o1; > wire [4:0] o0; > assign b=5'b10110;//-10 > assign a=0; > assign o0=(b >>> 2);//line7: shift arithmetic > assign o1=(b >> 2); //line8: shift > endmodule > > but o1=o0 i don' so >>> and >> is the same? No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and <<< are available in Verilog-2001 so make sure you compile in Verilog-2001 (refer to the manual of your simulator).

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3/13/2014 12:56:26 PM

Vince wrote: > "a.h e.j" a �crit : >> thanks Nikolaos Kavvadias >> my code is: >> module my(b,o0,o1); >> input [4:0] b; >> output [4:0] o0,o1; >> wire [4:0] o0; >> assign b=5'b10110;//-10 >> assign a=0; >> assign o0=(b >>> 2);//line7: shift arithmetic >> assign o1=(b >> 2); //line8: shift >> endmodule >> >> but o1=o0 i don' so >>> and >> is the same? > > No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and > <<< are available in Verilog-2001 so make sure you compile in Verilog-2001 > (refer to the manual of your simulator). I wasn't aware that Modelsim didn't support this basic feature of Verilog 2001 unless you have a very old version. However it was my understanding that >>> would only operate correctly (i.e. replicate the MSB) if the argument to be shifted was signed. -- Gabor

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3/13/2014 5:50:05 PM

Hi AHEJ what are you trying to solve/achieve? I can see an attempt to the solution = but not a statement of the problem. Best regards Nikolaos Kavvadias PS: Your code syntactically passes through Icarus Verilog (which supports V= erilog-2001). > "a.h e.j" a =E9crit :=20 >=20 > > thanks Nikolaos Kavvadias >=20 > > my code is: >=20 > > module my(b,o0,o1); >=20 > > input [4:0] b; >=20 > > output [4:0] o0,o1; >=20 > > wire [4:0] o0; >=20 > > assign b=3D5'b10110;//-10 >=20 > > assign a=3D0; >=20 > > assign o0=3D(b >>> 2);//line7: shift arithmetic >=20 > > assign o1=3D(b >> 2); //line8: shift >=20 > > endmodule >=20 > >=20 >=20 > > but o1=3Do0 i don' so >>> and >> is the same? >=20 >=20 >=20 > No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>>= and >=20 > <<< are available in Verilog-2001 so make sure you compile in Verilog-200= 1 >=20 > (refer to the manual of your simulator).

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3/13/2014 8:11:20 PM

Hello everyone, when I using verilog-in in ic5141,it appears a sytanx error ">>> error". my verilog code have arithmetic shift >>> adn <<<,which is the new characteristic of verilog-2001. and I do verilog-in operation in behavior RTL,my question is :how to fix this error?and still:does ic5141 verilog-in function support verilog2001 verison's arithemetic shift operationor ">>>" and "<<<" ? thank you. On 8 13 , 1 09 , ponderboy <cqu_...@yahoo.com.cn> wrote: could anybody help me please. > He...

Hi all, I'm seeing some mismatching results for a Verilog 2001 arithmetic shift operator in NCVerilog and since I don't have a Verilog 2001 LRM handy, I thought I'd ask to experts to see if they knew what the LRM specified in this regards. I originally found this when we had an RTL/gates simulation mismatch, but have extracted the problem to the following Verilog code: module ArithmeticShiftTest; reg signed [31:0] in; reg [5:0] shift; reg signed [31:0] out; //calculate arithmetic barrel shift right always@(*) out = in >>> shift; ...

is there an equivalent way in verilog to do this: The contents of the low-order 32-bit word of a number are shifted right, duplicating the sign-bit (bit 31) in the emptied bits It's so easy that I'm not sure I understand your meaning right. @clk reg A[31:0]= {A[31],A[31:1]} "rekz" <aditya15417@gmail.com> ??????:ade3aa13-3209-4ba6-b534-87c624d542e8@x22g2000yqx.googlegroups.com... > is there an equivalent way in verilog to do this: > > The contents of the low-order 32-bit word of a number are shifted > right, duplicating the sign-bit (bit 3...

I was looking up the shift operator in VHDL since I seldom use it and saw that there is both a shift left logical and a shift left arithmetic. The logic shift left shifts in zeros and the arithmetic shift left shifts in the value of the lsb. I remember from school how a shift right can be logical or arithmetic in order to implement signed and unsigned arithmetic. But when shifting left, I have always used a single shift operator, the logical shift. If an arithmetic left shift is used, it gives a valid result for some values, assuming that the "valid" result is the same as multipl...

Hello, Can anyone suggest me operator to perform arithmetic shift in C? May it be for a perticular compiler. Thank you in advance. Regards, Shailendra Le 15/06/2005 15:22, dans d8pa1r$s8d$1@ns2.fe.internet.bosch.com, ��Mehta Shailendrakumar�� <shailendrakumar.mehta@de.bosch.com> a �crit�: > Hello, > Can anyone suggest me operator to perform arithmetic shift in C? > May it be for a perticular compiler. > > Thank you in advance. > > Regards, > Shailendra > > Ops are << and >>. * n << k = n * 2^k * n >> k = n / 2...

hi everybody, how i can traslate this line in C varA = (varA<<4) + varB; in VHDL language???? wrong exemple varA <= (varA sll 4) + varB; My problem is the shift "<<" i try with SHL, sll, ecc. but i cant compile the vhdl because there is some error. I have include librerie std_logic_arith "use IEEE.std_logic_arith.all;" but have this error: Operator "sll" is not defined for such operands. Undefined type of expression. Assignment target incompatible with right side. Expected type "std_logic_vector". i have tray with different type: s...

I'm currently rewriting some numerical code for MISRA compliance. Signed shifts are not defined by the C-standard, and the code-checker complaints. Well - no big surprise here. I knew that and did it nevertheless. Now I have to rewrite. But do you do if you need them anyway? I need *lots* of them, so in despair I've just created this monster of unreadable code: int ArithmeticShiftRight (int value, unsigned int shift) { if (shift) { /* Get unsigned version of value to work with */ unsigned int x = (unsigned int) value; /* replicate the sign-bit of value int...

Does anybody know how to perform an arithmetic bit shift right in Matlab? I tried using bitshift, but it cuts off the decimal points (i.e. bitshift(6.625,-2) = 1, but it should be 1.75). I have also tried to get the binary number using the bitget function, but it too cuts off the decimal points and returns (1100 or 6). Thanks in advance. "John Ryan" <jballgame20@aol.com> writes: > Does anybody know how to perform an arithmetic bit shift right in > Matlab? I tried using bitshift, but it cuts off the decimal points > (i.e. bitshift(6.625,-2) = 1, but it should be 1.75)...

Hi, In the verilog spec IEEE P1364-2005/D3 section 4.1.3 "Using integer numbers in expressions", there are the following examples about signed arithmetic (see below). Can someone explain the second example? Assuming that their results are printed in base 10, I cannot figure out how the result is 1431655761. Thanks in advance, Mike -------------------------------------------------- integer IntA; IntA = -12 / 3; // The result is -4. IntA = -'d 12 / 3; // The result is 1431655761. IntA = -'sd 12 / 3; // The result is -4. IntA = -4'sd 12 / 3; // -4'...

Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl: bottom" How to write a vhdl configuration to select the file for the bottom instantiation? Rakesh YC try ...

I understand Verilog 2001 added the ">>>" operator for sign extension right shift. But how does it work? I was implementing a shifter unit as part of an ALU. I had done the following: assign #1 rarithmetic = b >>> shiftamount; where b and shiftamount were both input [31:0] vectors. However, the sign extension does not occur. I had b = 0xd1200000 and the result was 0x0000d120 instead of 0xffffd120. I know there is also the "signed" keyword but it didn't seem to have any effect when I tried "input signed [31:0] ...". What am I doing...

Sorry for my poor english :/ I want to divide unsigned binary integers using non-restoring division! I have found te algorithm here: http://stackoverflow.com/questions/12133810/non-restoring-division-algorithm I have implemented the algorithm on verilog.But for some reason the module does not work correct! The module code: I have comented where i think the mistake is! module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a, b); reg[7:0] A; reg[7:0] B; reg[7:0] Q; reg[7:0] M; reg[7:0] N; always @(*) begin A=8&#...

Hi All, I need Shift register and LFSR verilog code...Please forward them if you have written one earlier. Thanks Sridhar If you google "lsfr verilog", you would come up with many choices. One of the first entries I came up with is http://www.doe.carleton.ca/~jknight/97.478/97.478_03F/Advdig5cirJ.pdf, which probably tells you more than you will ever care to know about LFSRs. It is straightforward to modify the LSFR code to just be a shift register. Have fun with the rest of your homework. Jason "Sridhar_Gadda" <sridhargadda@...

Sorry for my poor english :/ I want to divide unsigned binary integers using non-restoring division! I have found te algorithm here: http://stackoverflow.com/questions/12133810/non-restoring-division-algorithm I have implemented the algorithm on verilog.But for some reason the module does not work correct! The module code: I have comented where i think the mistake is! module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a, b); reg[7:0] A; reg[7:0] B; reg[7:0] Q; reg[7:0] M; reg[7:0] N; always @(*) begin A=8&#...

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