f



shift right arithmetic

is there an equivalent way in verilog to do this:

The contents of the low-order 32-bit word of a number are shifted
right, duplicating the sign-bit (bit 31) in the emptied
bits
0
rekz
3/8/2010 12:03:54 AM
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It's so easy that I'm not sure I understand your meaning right.

@clk
reg A[31:0]= {A[31],A[31:1]}

"rekz" <aditya15417@gmail.com> 
??????:ade3aa13-3209-4ba6-b534-87c624d542e8@x22g2000yqx.googlegroups.com...
> is there an equivalent way in verilog to do this:
>
> The contents of the low-order 32-bit word of a number are shifted
> right, duplicating the sign-bit (bit 31) in the emptied
> bits 


0
Shenzhi
3/8/2010 4:06:34 AM
rekz wrote:
> is there an equivalent way in verilog to do this:
> 
> The contents of the low-order 32-bit word of a number are shifted
> right, duplicating the sign-bit (bit 31) in the emptied
> bits

Are you looking for the >>> operator? In reality there are many ways to 
do this. The >>> operator only works if the value is signed. For 
unsigned values you need to either cast it signed or resort to bit 
manipulation like the previous poster showed.

Cary
0
Cary
3/8/2010 7:54:35 AM
On Sun, 07 Mar 2010 23:54:35 -0800, "Cary R." wrote:

>The >>> operator only works if the value is signed.

WHOAH!  How many times have I ranted about this...?

Let's try again.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The >>> operator gives sign-extended shift only
if it is used in a signed EXPRESSION.  
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The signedness of its argument is not the whole
story.  (Cary, I'm sure you are perfectly aware
of that.  But it is a HUGE pitfall for novices
and I make no apology for raising it again.)

A few examples, in the form of a quiz -
answers later...

  reg signed [7:0] S1;
  reg signed [7:0] S2;
  reg [7:0] U1; // unsigned
  reg [7:0] U2; // unsigned

For each of the following examples, decide whether
the >>> operator does sign-extended (signed) or 
zero-fill (unsigned) shifting:

initial begin
  ... <assume we have sensible values in the variables> ...
  S2 = S1 >>> 3;         // example 1
  U1 = S1 >>> 3;         // example 2
  S2 = U1 + (S1 >>> 3);  // example 3
  U1 = S2 + (S1 >>> 3);  // example 4
  S2 = S1 >>> U1;        // example 5
  S2 = $signed(U1 >>> 3);  // example 6
  S2 = U1 + $signed(S1 >>> 3);  // example 7
  S2 = U1 + $unsigned(S1 >>> 3);  // example 8
  S2 = S1[7:0] >>> 3;    // example 9
end

Answers below..........










(soon)














(just a few more lines down)














  S2 = S1 >>> 3;         // example 1
           signed shift (all operands are signed)

  U1 = S1 >>> 3;         // example 2
           signed shift (signing of assignment target
           doesn't affect signedness of expression)

  S2 = U1 + (S1 >>> 3);  // example 3
           UNSIGNED shift (operand U1 is unsigned, forces
           the whole expression to be unsigned despite S1)

  U1 = S2 + (S1 >>> 3);  // example 4
           signed shift (again U1 doesn't affect signing)

  S2 = S1 >>> U1;        // example 5
           signed shift (unsigned shift count doesn't 
           affect the signed expression context)

  S2 = $signed(U1 >>> 3);  // example 6
           UNSIGNED shift ($signed creates a signed 
           result, but does not affect the signing of its
           argument expression)

  S2 = U1 + $signed(S1 >>> 3);  // example 7
           signed shift ($signed, or ANY function, protects
           its argument expression from the unsigned context)

  S2 = U1 + $unsigned(S1 >>> 3);  // example 8
           signed shift ($unsigned does not affect the signing
           of its argument expression)

  S2 = S1[7:0] >>> 3;    // example 9
           UNSIGNED shift (a part select is invariably unsigned)

Glad we got that cleared up...
-- 
Jonathan Bromley
0
Jonathan
3/8/2010 10:29:14 AM
On Mar 8, 3:29=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sun, 07 Mar 2010 23:54:35 -0800, "Cary R." wrote:
> >The >>> operator only works if the value is signed.
>
> WHOAH! =A0How many times have I ranted about this...?
>
> Let's try again.
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> The >>> operator gives sign-extended shift only
> if it is used in a signed EXPRESSION. =A0
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> The signedness of its argument is not the whole
> story. =A0(Cary, I'm sure you are perfectly aware
> of that. =A0But it is a HUGE pitfall for novices
> and I make no apology for raising it again.)
>
> A few examples, in the form of a quiz -
> answers later...
>
> =A0 reg signed [7:0] S1;
> =A0 reg signed [7:0] S2;
> =A0 reg [7:0] U1; // unsigned
> =A0 reg [7:0] U2; // unsigned
>
> For each of the following examples, decide whether
> the >>> operator does sign-extended (signed) or
> zero-fill (unsigned) shifting:
>
> initial begin
> =A0 ... <assume we have sensible values in the variables> ...
> =A0 S2 =3D S1 >>> 3; =A0 =A0 =A0 =A0 // example 1
> =A0 U1 =3D S1 >>> 3; =A0 =A0 =A0 =A0 // example 2
> =A0 S2 =3D U1 + (S1 >>> 3); =A0// example 3
> =A0 U1 =3D S2 + (S1 >>> 3); =A0// example 4
> =A0 S2 =3D S1 >>> U1; =A0 =A0 =A0 =A0// example 5
> =A0 S2 =3D $signed(U1 >>> 3); =A0// example 6
> =A0 S2 =3D U1 + $signed(S1 >>> 3); =A0// example 7
> =A0 S2 =3D U1 + $unsigned(S1 >>> 3); =A0// example 8
> =A0 S2 =3D S1[7:0] >>> 3; =A0 =A0// example 9
> end
>
> Answers below..........
>
> (soon)
>
> (just a few more lines down)
>
> =A0 S2 =3D S1 >>> 3; =A0 =A0 =A0 =A0 // example 1
> =A0 =A0 =A0 =A0 =A0 =A0signed shift (all operands are signed)
>
> =A0 U1 =3D S1 >>> 3; =A0 =A0 =A0 =A0 // example 2
> =A0 =A0 =A0 =A0 =A0 =A0signed shift (signing of assignment target
> =A0 =A0 =A0 =A0 =A0 =A0doesn't affect signedness of expression)
>
> =A0 S2 =3D U1 + (S1 >>> 3); =A0// example 3
> =A0 =A0 =A0 =A0 =A0 =A0UNSIGNED shift (operand U1 is unsigned, forces
> =A0 =A0 =A0 =A0 =A0 =A0the whole expression to be unsigned despite S1)
>
> =A0 U1 =3D S2 + (S1 >>> 3); =A0// example 4
> =A0 =A0 =A0 =A0 =A0 =A0signed shift (again U1 doesn't affect signing)
>
> =A0 S2 =3D S1 >>> U1; =A0 =A0 =A0 =A0// example 5
> =A0 =A0 =A0 =A0 =A0 =A0signed shift (unsigned shift count doesn't
> =A0 =A0 =A0 =A0 =A0 =A0affect the signed expression context)
>
> =A0 S2 =3D $signed(U1 >>> 3); =A0// example 6
> =A0 =A0 =A0 =A0 =A0 =A0UNSIGNED shift ($signed creates a signed
> =A0 =A0 =A0 =A0 =A0 =A0result, but does not affect the signing of its
> =A0 =A0 =A0 =A0 =A0 =A0argument expression)
>
> =A0 S2 =3D U1 + $signed(S1 >>> 3); =A0// example 7
> =A0 =A0 =A0 =A0 =A0 =A0signed shift ($signed, or ANY function, protects
> =A0 =A0 =A0 =A0 =A0 =A0its argument expression from the unsigned context)
>
> =A0 S2 =3D U1 + $unsigned(S1 >>> 3); =A0// example 8
> =A0 =A0 =A0 =A0 =A0 =A0signed shift ($unsigned does not affect the signin=
g
> =A0 =A0 =A0 =A0 =A0 =A0of its argument expression)
>
> =A0 S2 =3D S1[7:0] >>> 3; =A0 =A0// example 9
> =A0 =A0 =A0 =A0 =A0 =A0UNSIGNED shift (a part select is invariably unsign=
ed)
>
> Glad we got that cleared up...
> --
> Jonathan Bromley

wait is there a >>> operation in verilog? lol.. didn't know about
that... that's what I've been looking for
0
rekz
3/8/2010 2:35:48 PM
On Mon, 8 Mar 2010 06:35:48 -0800 (PST), rekz wrote:

>wait is there a >>> operation in verilog?

Yup, it's been there since 2001.

You did *read* the rest of my post, right?  So you
know how >>> can rather easily turn around and
bite you in the arse?  'coz if you don't know those
things, you will end up with a very sore backside.

amicalement
-- 
Jonathan Bromley
0
Jonathan
3/8/2010 9:18:04 PM
On Mar 8, 2:18=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Mon, 8 Mar 2010 06:35:48 -0800 (PST), rekz wrote:
> >wait is there a >>> operation in verilog?
>
> Yup, it's been there since 2001.
>
> You did *read* the rest of my post, right? =A0So you
> know how >>> can rather easily turn around and
> bite you in the arse? =A0'coz if you don't know those
> things, you will end up with a very sore backside.
>
> amicalement
> --
> Jonathan Bromley

Yes I did read your post... I think I'll avoid using the >>> then...
as the result needs to be stored in a signed variable right for this
to make it happen? While my result should be stored in a reg[31:0]
Result
0
rekz
3/9/2010 3:20:54 PM
Jonathan Bromley wrote:

> The signedness of its argument is not the whole
> story.  (Cary, I'm sure you are perfectly aware
> of that.  But it is a HUGE pitfall for novices
> and I make no apology for raising it again.)

Yes I probably should have said value/expression and yes I know exactly 
how this works, I have two of them in the RTL for the chip we just 
shipped. You also need to understand this was at the end of a 15 hour 
day and my average days had not been that much shorter, so my thought 
was probably a bit scattered.

For some more fun add the following after example 4 (concatenation).
   S2 = U1 + {S1 >>> 3};
   U1 = S2 + {S1 >>> 3};

Cary
0
Cary
3/10/2010 6:56:58 PM
Reply: