sign extension in verilog - comp.lang.verilog

I would like to design a 16 to 32-bit sign extension unit. I would like to preserve the number's sign (positive/negative). So I guess after I append digits to the MSB then I would need to take care of the sign's, how could I do this in verilog?

On Jan 27, 4:23=A0pm, rekz <aditya15...@gmail.com> wrote: > I would like to design a 16 to 32-bit sign extension unit. I would > like to preserve the number's sign (positive/negative). So I guess > after I append digits to the MSB then I would need to take care of the > sign's, how could I do this in verilog? is it just as simple as this: module SignExtension(a, result); input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result =3D { 16{a[31]}, a }; endmodule

This is a multi-part message in MIME format. ----------------275652565738620419 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit On 2010-01-27 15:30:27 -0800, rekz said: > On Jan 27, 4:23�pm, rekz <aditya15...@gmail.com> wrote: >> I would like to design a 16 to 32-bit sign extension unit. I would >> like to preserve the number's sign (positive/negative). So I guess >> after I append digits to the MSB then I would need to take care of the >> sign's, how could I do this in verilog? > > is it just as simple as this: > > module SignExtension(a, result); > > input [15:0] a; // 16-bit input > output [31:0] result; // 32-bit output > > assign result = { 16{a[31]}, a }; This should be assign result = { 16{a[15]}, a }; Basically, you just take the MSB of the input and repeat it to fill to the left. > > endmodule ----------------275652565738620419 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <meta http-equiv="Content-Style-Type" content="text/css"> <title></title> <meta name="Generator" content="Cocoa HTML Writer"> <meta name="CocoaVersion" content="1038.25"> <style type="text/css"> p.p1 {margin: 0.0px 0.0px 0.0px 0.0px; line-height: 15.0px; font: 12.0px Helvetica} p.p2 {margin: 0.0px 0.0px 0.0px 0.0px; line-height: 15.0px; font: 12.0px Helvetica; min-height: 14.0px} p.p3 {margin: 0.0px 0.0px 0.0px 12.0px; line-height: 14.0px; font: 12.0px Helvetica; color: #1b0494} p.p4 {margin: 0.0px 0.0px 0.0px 24.0px; font: 12.0px Helvetica; color: #4e8f00} p.p5 {margin: 0.0px 0.0px 0.0px 12.0px; font: 12.0px Helvetica; color: #1b0494; min-height: 14.0px} p.p6 {margin: 0.0px 0.0px 0.0px 12.0px; font: 12.0px Helvetica; color: #1b0494} p.p7 {margin: 0.0px 0.0px 0.0px 0.0px; line-height: 14.0px; font: 12.0px Helvetica; min-height: 14.0px} p.p8 {margin: 0.0px 0.0px 0.0px 0.0px; line-height: 14.0px; font: 12.0px Helvetica; color: #1b0494} p.p9 {margin: 0.0px 0.0px 0.0px 0.0px; line-height: 14.0px; font: 12.0px Helvetica; color: #1b0494; min-height: 14.0px} span.s1 {color: #000000} </style> </head> <body> On 2010-01-27 15:30:27 -0800, rekz said: On Jan 27, 4:23�pm, rekz <aditya15...@gmail.com> wrote: I would like to design a 16 to 32-bit sign extension unit. I would like to preserve the number's sign (positive/negative). So I guess after I append digits to the MSB then I would need to take care of the sign's, how could I do this in verilog? is it just as simple as this: module SignExtension(a, result); input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result = { 16{a[31]}, a }; This should be assign result = { 16{a[15]}, a }; Basically, you just take the MSB of the input and repeat it to fill to the left. endmodule </body> </html> ----------------275652565738620419--

On Jan 27, 5:07=A0pm, David Rogoff <da...@therogoffs.com> wrote: > On 2010-01-27 15:30:27 -0800, rekz said: > > > On Jan 27, 4:23=A0pm, rekz <aditya15...@gmail.com> wrote: > >> I would like to design a 16 to 32-bit sign extension unit. I would > >> like to preserve the number's sign (positive/negative). So I guess > >> after I append digits to the MSB then I would need to take care of the > >> sign's, how could I do this in verilog? > > > is it just as simple as this: > > > module SignExtension(a, result); > > > input [15:0] a; // 16-bit input > > output [31:0] result; // 32-bit output > > > assign result =3D { 16{a[31]}, a }; > > This should be assign result =3D { 16{a[15]}, a }; > > Basically, you just take the MSB of the input and repeat it to fill to > the left. > > > > > endmodule > > And doing this will preserve the sign of the numbers?? Why?

David Rogoff wrote: > On 2010-01-27 15:30:27 -0800, rekz said: > >> On Jan 27, 4:23 pm, rekz <aditya15...@gmail.com> wrote: >> I would like to design a 16 to 32-bit sign extension unit. I would >> like to preserve the number's sign (positive/negative). So I guess >> after I append digits to the MSB then I would need to take care of the >> sign's, how could I do this in verilog? >> >> is it just as simple as this: >> >> module SignExtension(a, result); >> input [15:0] a; // 16-bit input >> output [31:0] result; // 32-bit output >> >> assign result = { 16{a[31]}, a }; >> >> endmodule > > This should be assign result = { 16{a[15]}, a }; > > Basically, you just take the MSB of the input and repeat it to fill to > the left. Or use a signed right expression and the tools should take care of it for you. There can be some subtlety with this, but it does work when you understand the rules. Cary

rekz wrote: > On Jan 27, 5:07 pm, David Rogoff <da...@therogoffs.com> wrote: >> On 2010-01-27 15:30:27 -0800, rekz said: >> >>> On Jan 27, 4:23 pm, rekz <aditya15...@gmail.com> wrote: >>>> I would like to design a 16 to 32-bit sign extension unit. I would >>>> like to preserve the number's sign (positive/negative). So I guess >>>> after I append digits to the MSB then I would need to take care of the >>>> sign's, how could I do this in verilog? >>> is it just as simple as this: >>> module SignExtension(a, result); >>> input [15:0] a; // 16-bit input >>> output [31:0] result; // 32-bit output >>> assign result = { 16{a[31]}, a }; >> This should be assign result = { 16{a[15]}, a }; >> >> Basically, you just take the MSB of the input and repeat it to fill to >> the left. >> >> >> >>> endmodule >> > > And doing this will preserve the sign of the numbers?? Why? Read up on twos-complement numbers! Cary

On Wed, 27 Jan 2010 16:44:28 -0800, "Cary R." wrote: >> Basically, you just take the MSB of the input and >> repeat it to fill to the left. > >Or use a signed right expression and the tools should take >care of it for you. There can be some subtlety with this, Nominated for Understatement Of The Year. > but it does work when you understand the rules. And spectacularly and mysteriously fails to work when you don't, or when you do understand but you forget one of the many Gotchas. I would very strongly urge beginners to steer clear of Verilog signed arithmetic - especially beginners like the OP whose grasp of twos-complement seems shaky :-) -- Jonathan Bromley

Jonathan Bromley wrote: > On Wed, 27 Jan 2010 16:44:28 -0800, "Cary R." wrote: > >>> Basically, you just take the MSB of the input and >>> repeat it to fill to the left. >> Or use a signed right expression and the tools should take >> care of it for you. There can be some subtlety with this, > > Nominated for Understatement Of The Year. > >> but it does work when you understand the rules. > > And spectacularly and mysteriously fails to work when you > don't, or when you do understand but you forget one of > the many Gotchas. > > I would very strongly urge beginners to steer clear of > Verilog signed arithmetic - especially beginners like > the OP whose grasp of twos-complement seems shaky :-) Correct advice, but now those poor beginners must be really confused :-) They might intuitively think that handling negative integers is a common task that should be simple. My advice to them: think outside the box for a while, before attempting to become a Verilog guru. Perhaps your intuition is right, and it's the HDL language designers that have it all wrong. Perhaps there is a better way. To start thinking outside the box, read this: http://www.jandecaluwe.com/hdldesign/counting.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com

Jonathan Bromley wrote: > And spectacularly and mysteriously fails to work when you > don't, or when you do understand but you forget one of > the many Gotchas. Been there seen that, but sometime not using it is even more painful. For example in my current design I have a signed signal that represents a correction value as 0.2dB per step. This needs to be expanded to 0.15dB per step with the correct rounding. Then because of a mistake in the polarity of the analog system I need to negate the result. With signed registers and arithmetic this isn't too bad to look at and understand. Well the rounding of negative values is a bit complicated, but that's completely independent and I added ample comments. ;-) > I would very strongly urge beginners to steer clear of > Verilog signed arithmetic - especially beginners like > the OP whose grasp of twos-complement seems shaky :-) I won't disagree with this, but they need to understand that alternatives exist. Otherwise they won't understand perfectly valid and working code. Cary

rekz wrote: > assign result = { 16{a[31]}, a }; As a side note this is invalid replication syntax. This should be written as. assign result = { {16{a[31]}}, a }; Notice the replication is enclosed in {}. cver does accept this invalid syntax, but don't count on it being portable. Cary

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