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signed arithmetic example from verilog spec

Hi,

In the verilog spec IEEE P1364-2005/D3 section
4.1.3 "Using integer numbers in expressions",
there are the following examples about signed
arithmetic (see below).

Can someone explain the second example?
Assuming that their results are printed in base 10,
I cannot figure out how the result is 1431655761.

Thanks in advance,
Mike
--------------------------------------------------

integer IntA;
IntA = -12 / 3; // The result is -4.
IntA = -'d 12 / 3; // The result is 1431655761.
IntA = -'sd 12 / 3; // The result is -4.
IntA = -4'sd 12 / 3; // -4'sd12 is the negative of the 4-bit
// quantity 1100, which is -4. -(-4) = 4.
// The result is 1.

0
Mike
8/23/2007 8:41:37 PM
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Because the value 12 is unsigned, the negative is also unsigned.  The 
integer defaults to 32 bits so the value -'d12 is -32'd12 or (2^32)-12. 
This very large number is why the result is so large.

"Mike" <hammeron56@yahoo.com> wrote in message 
news:1187901697.679177.198700@m37g2000prh.googlegroups.com...
> Hi,
>
> In the verilog spec IEEE P1364-2005/D3 section
> 4.1.3 "Using integer numbers in expressions",
> there are the following examples about signed
> arithmetic (see below).
>
> Can someone explain the second example?
> Assuming that their results are printed in base 10,
> I cannot figure out how the result is 1431655761.
>
> Thanks in advance,
> Mike
> --------------------------------------------------
>
> integer IntA;
> IntA = -12 / 3; // The result is -4.
> IntA = -'d 12 / 3; // The result is 1431655761.
> IntA = -'sd 12 / 3; // The result is -4.
> IntA = -4'sd 12 / 3; // -4'sd12 is the negative of the 4-bit
> // quantity 1100, which is -4. -(-4) = 4.
> // The result is 1.
> 


0
John_H
8/23/2007 9:02:28 PM
The previous reply does not answer my question.  However,
it seems that I have solved my own problem:

-'d 12 / 3
=(-12)/3
=(-0x0000000c/0x00000003)
=( 0xfffffff4/0x00000003)
=  0x55555551
=1,431,655,761

On Aug 23, 5:02 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
> Because the value 12 is unsigned, the negative is also unsigned.  The
> integer defaults to 32 bits so the value -'d12 is -32'd12 or (2^32)-12.
> This very large number is why the result is so large.
>
> "Mike" <hammero...@yahoo.com> wrote in message
>
> news:1187901697.679177.198700@m37g2000prh.googlegroups.com...
>
> > Hi,
>
> > In the verilog spec IEEE P1364-2005/D3 section
> > 4.1.3 "Using integer numbers in expressions",
> > there are the following examples about signed
> > arithmetic (see below).
>
> > Can someone explain the second example?
> > Assuming that their results are printed in base 10,
> > I cannot figure out how the result is 1431655761.
>
> > Thanks in advance,
> > Mike
> > --------------------------------------------------
>
> > integer IntA;
> > IntA = -12 / 3; // The result is -4.
> > IntA = -'d 12 / 3; // The result is 1431655761.
> > IntA = -'sd 12 / 3; // The result is -4.
> > IntA = -4'sd 12 / 3; // -4'sd12 is the negative of the 4-bit
> > // quantity 1100, which is -4. -(-4) = 4.
> > // The result is 1.


0
Mike
8/24/2007 12:38:53 AM
In what way was my response incomplete?

Mike wrote:
> The previous reply does not answer my question.  However,
> it seems that I have solved my own problem:
> 
> -'d 12 / 3
> =(-12)/3
> =(-0x0000000c/0x00000003)
> =( 0xfffffff4/0x00000003)
> =  0x55555551
> =1,431,655,761
> 
> On Aug 23, 5:02 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
>> Because the value 12 is unsigned, the negative is also unsigned.  The
>> integer defaults to 32 bits so the value -'d12 is -32'd12 or (2^32)-12.
>> This very large number is why the result is so large.
>>
>> "Mike" <hammero...@yahoo.com> wrote in message
>>
>> news:1187901697.679177.198700@m37g2000prh.googlegroups.com...
>>
>>> Hi,
>>> In the verilog spec IEEE P1364-2005/D3 section
>>> 4.1.3 "Using integer numbers in expressions",
>>> there are the following examples about signed
>>> arithmetic (see below).
>>> Can someone explain the second example?
>>> Assuming that their results are printed in base 10,
>>> I cannot figure out how the result is 1431655761.
>>> Thanks in advance,
>>> Mike
>>> --------------------------------------------------
>>> integer IntA;
>>> IntA = -12 / 3; // The result is -4.
>>> IntA = -'d 12 / 3; // The result is 1431655761.
>>> IntA = -'sd 12 / 3; // The result is -4.
>>> IntA = -4'sd 12 / 3; // -4'sd12 is the negative of the 4-bit
>>> // quantity 1100, which is -4. -(-4) = 4.
>>> // The result is 1.
0
John_H
8/24/2007 3:56:09 AM
On Thu, 23 Aug 2007 17:38:53 -0700, Mike <hammeron56@yahoo.com> wrote:

>The previous reply does not answer my question. 

Yes it does

>However,
>it seems that I have solved my own problem:
>
>-'d 12 / 3
>=(-12)/3

Technically, this isn't the case in Verilog; "-'d12" is not a "signed
negative number", but "-12" is. They both have the same bit value,
though.

>=( 0xfffffff4/0x00000003)
>=  0x55555551
>=1,431,655,761

That's what John said; the unsigned representation of -12, in 32 bits,
is 2^32 - 12, or 0xfffffff4.

Actually, I think the LRM example is technically incorrect. The result
is only true if the simulator chooses to store unsized numbers as 32
bits, although I imagine that most, if not all of them, do.

Evan
0
Evan
8/24/2007 6:17:22 PM
Evan Lavelle wrote:
>
> Technically, this isn't the case in Verilog; "-'d12" is not a "signed
> negative number", but "-12" is. They both have the same bit value,
> though.

Yes, the key is how that bit value is interpreted.  Sometimes that is
purely conceptual, but sometimes the interpretation really matters.
In this case, that interpretation occurs when the / operator does an
unsigned division rather than a signed one, which gives a different
bit value for the result.


> That's what John said; the unsigned representation of -12, in 32 bits,
> is 2^32 - 12, or 0xfffffff4.
>
> Actually, I think the LRM example is technically incorrect. The result
> is only true if the simulator chooses to store unsized numbers as 32
> bits, although I imagine that most, if not all of them, do.

Agreed, since Verilog only requires unsized numbers to be at least 32
bits.

In SystemVerilog, integers have been changed to 32 bits instead of at
least 32 bits.  And since the Verilog LRM states that unsized numbers
are the same size as integers, that would make unsized numbers exactly
32 bits also.

0
sharp
8/24/2007 7:20:24 PM
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Evan Lavelle wrote:
>> =( 0xfffffff4/0x00000003)
>> =  0x55555551
>> =1,431,655,761
> 
> That's what John said; the unsigned representation of -12, in 32 bits,
> is 2^32 - 12, or 0xfffffff4.
> 
> Actually, I think the LRM example is technically incorrect. The result
> is only true if the simulator chooses to store unsized numbers as 32
> bits, although I imagine that most, if not all of them, do.

At least one does not;-)

- --
Steve Williams                "The woods are lovely, dark and deep.
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0
Stephen
8/30/2007 8:57:39 PM
Stephen Williams <spamtrap@icarus.com> writes:

> Evan Lavelle wrote:
>>> =( 0xfffffff4/0x00000003)
>>> =  0x55555551
>>> =1,431,655,761
>> 
>> That's what John said; the unsigned representation of -12, in 32 bits,
>> is 2^32 - 12, or 0xfffffff4.
>> 
>> Actually, I think the LRM example is technically incorrect. The result
>> is only true if the simulator chooses to store unsized numbers as 32
>> bits, although I imagine that most, if not all of them, do.
>
> At least one does not;-)

I know of a 2nd one, but one that most readers won't ever encounter
since it is for strictly for in-house use.
0
Chris
8/31/2007 8:26:10 PM
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