SystemVerilog cross-module reference resolution error
I am developing some testbench code and I am seeing a cross-module resolution error. Specifically, Error-[XMRE] Cross-module reference resolution error Cross module resolution failed. Originating module 'top_level_program'. " BfmPhy.sv ", 308: this.cmdTable cmdTable is an array of 'cmd' objects. The table is declared in a parent class and is being used in a derived class. When trying to index into the cmdTable with the following code fragement, I see the error. cmdTable(acrtag).copy ...

cross-compiling python-2.5.1 for PPC, error in Modules/unicodedata.o
not sure if this is the right list for this, but it's a starting point. i'm using a wind river linux development environment to build a full system for a powerpc board, and that includes cross-compiling python-2.5.1 for ppc. the compile fails thusly: powerpc-wrs-linux-gnu-ppc_e500v2-glibc_std-gcc -shared Modules/unicodedata.o -o Modules/unicodedata.so Modules/unicodedata.o: file not recognized: File truncated collect2: ld returned 1 exit status Makefile:1159: *** [Modules/unicodedata.so] Error 1 .... snip ... #0 Modules/unicodedata.so at /home/rpjday/workspace/8548_prj/build/...

4.2.52 compile error on C++ module on AIX 5.2 using gcc 3.3.2
Would someone happen to have some ideas as why this is getting an error. Get the same problem using IBM's C compiler v 6.0. Thanks /bin/sh ./libtool --mode=compile g++ -c -I. -I../dist/.. -D_THREAD_SAFE -O2 ../dist/../cxx/cxx_d b.cpp g++ -c -I. -I../dist/.. -D_THREAD_SAFE -O2 ../dist/../cxx/cxx_db.cpp -DPIC -o .libs/cxx_db.o In file included from /cmDevTest/Dev/local/bin/../include/c++/3.3.2/powerpc-ibm-aix5.2.0.0/bits/c ++io.h:35, from /cmDevTest/Dev/local/bin/../include/c++/3.3.2/bits/fpos.h:44, from /cmDevTest/Dev/local/bin/../include/c++/3.3.2/iosfwd:49, from /cmDevTest/Dev/local/bin/../include/c++/3.3.2/ios:44, from /cmDevTest/Dev/local/bin/../include/c++/3.3.2/ostream:45, from /cmDevTest/Dev/local/bin/../include/c++/3.3.2/iostream:45, from db_cxx.h:56, from ../cxx/cxx_db.cpp:17: /cmDevTest/Dev/local/bin/../include/c++/3.3.2/cstdio:108: error: `fgetpos' not declared /cmDevTest/Dev/local/bin/../include/c++/3.3.2/cstdio:110: error: `fopen' not declared /cmDevTest/Dev/local/bin/../include/c++/3.3.2/cstdio:115: error: `freopen' not declared /cmDevTest/Dev/local/bin/../include/c++/3.3.2/cstdio:118: error: `fsetpos' not declared make: *** [cxx_db.lo] Error 1 aixth4(cmadmin)# nm -BCpg /usr/lib/libc.a | grep freopen 40284 T .freopen64 40764 T .freopen 262296 D freopen64 ...

Is it possible to have a parameterized verilog module name in verilog or systemverilog?
Hi, I am trying create verilog module that can support parameterized instance n= ame. I understand that the signal width and other such things can be parame= terized. But can we also parameterize the module instance name? In following code, I am curious if there is any way SomeDynamicInstanceName= can be parameterized also? I can try to use system verilog if that can hel= p here=20 My purpose is to be able to reuse the verilog gmon module (generic verilog = module) for various types of signals. But for a reason, I need to change t= he SomeDynamicInstanceName. I have control o...

problems with in 2.3.2 developed modules used with 2.2.2
Sorry for the long header of this mail ;-) Has anyone experienced modules developed in 2.3.2 (using IDLE and = PythonWin as IDE) don't work under 2.2.2.... I mean basic stuff like it = can not see classes from your .py file, so an import fails? It almost likes that in my case 2.2.2 doesn't like the file format = generated by IDLE or PythonWin in 2.3.2. Does someone know if this is a known problem? Vincent Try deleting the .pyc version of the file... maybe 2.2.2 doesn't realize that the magic number is wrong and that it should recompile from the .py source. Kevin. "Raa...

niHSDIO error in labview 8.2. error in niHSDIO Get Session Reference.vi
I get an error in the niHSDIO Get Session Reference.vi.  the error is on the wire from refnum to the refnum input of the register session function.  It says "This wire connects to a polymorphic terminal that cannot accept this datatype."     I've installed all the required drivers of the latest version: visa 3.4 ivi compliance package 2.5 NI-DAQmx83 NIHSDIO 1.4.2 measurement and automation 4.1   I still get this error. thanks kevin   Kevin, please verify that the error occurs within the blockdiagram i attached. If it does,...

Re: Help:Error msg[Routine xx of module yy could not be loaded] #2 #2
Ching Fang Chi <chingfang@GMAIL.COM> replied: > It's part of the project. My professor wants to see if we can call outside > dll in SAS program because he needs to do some special computations which > may not be available in SAS. Just about any 'special computations' can be done in a SAS data step or in SAS/IML as easily as outside SAS. So you may never need to go this route. In the meantime, we don't usually try to make people do the hard stuff in SAS three weeks after they first start programming. I think you'll want to look through the SAS-L archives f...

Error #2 #2
C:\Documents and Settings\rkg\Desktop\Qt Codes>make mingw32-make -f Makefile.Debug mingw32-make[1]: Entering directory `C:/Documents and Settings/rkg/ Desktop/Qt Co des' g++ -enable-stdcall-fixup -Wl,-enable-auto-import -Wl,-enable-runtime- pseudo-rel oc -mthreads -Wl -Wl,-subsystem,windows -o "debug\Qt Codes.exe" debug/ hello.o - L"c:\Qt\4.3.3\lib" -lmingw32 -lqtmaind -lQtGuid4 -lQtCored4 C:\MinGW\bin\..\lib\gcc\mingw32\3.4.2\..\..\..\..\mingw32\bin\ld.exe: cannot fin d -lqtmaind collect2: ld returned 1 exit status mingw32-make[1]: *** ["debug\Qt] Error 1 ming...

error 2 #2
ada yg bisa bantu gk..... file aku sering rusak "Fatal Manager Error 2" Gimana ya cara spy gk error lg???? ...

error #2 #2
my error during compilation Type: C >>>xlink.exe -NOEXPOBJ -MAP -FORCE:MULTIPLE -NOIMPLIB - subsystem:console -LIBPATH:"C:\xHB\lib" -LIBPATH:"C:\xHB\c_lib" - LIBPATH:"C:\xHB\c_lib\win" "TEST.obj" xhb.lib dbf.lib ntx.lib cdx.lib rmdbfcdx.lib activex.lib crt.lib kernel32.lib user32.lib winspool.lib ole32.lib oleaut32.lib odbc32.lib odbccp32.lib uuid.lib wsock32.lib ws2_32.lib wininet.lib advapi32.lib shlwapi.lib -out:"test.exe"<<< xLINK: error: Unresolved external symbol '_HB_FUN_BACKDROP'. xLINK: error: Unresolved e...

References to references #2
I'm getting an unforseen problem when I'm trying to compile code for older compilers. The following code compiles in clang 3.0 on a Mac: template <class Key> struct Foo { typedef Key& key_type; virtual Bar mapKey(const key_type& key) = 0; }; However, when I compile with gcc 4.1.2 on SUSE Linux, I get "cannot declare reference to 'Key&', specifically wrt to mapKey(). I'm trying to find the root cause of this: Is it a C++11-specifc thing, and thus barfing on gcc 4.1.2, which IIRC has no C++11 support? Is it simply that I am expecting...

LV 8.2.1 Error 66 or 1379 occured at open Application Reference. A LV 8.2.1
Hi, LV 8.2.1 Error 66 or 1379 occured at open Application Reference. A LV 8.2.1 Using: Application access an other LV application on an remote PC with Vi-Server Technology. (Based on MS OS Windows XP SP2 with all patches ...) With LabVIEW 8.2.1 it is not possible (exactly: with one PC it works, with other PCs, (identical regarding configuration of LabVIEW-Components), the described errors occured ... There is no problem with LV 7.1.1. ( If the VI-Server Configuration of the .exe will be done within the .ini -File...) The differences between LV 7.1.1 are in the .ini-File of the application reg...

2 modules #2
i have 2 modules. one i call 'main' one is called 'counter' which is instantiated in main. main has... clk input counter_input [7:0] output counter has... clk input counter output (i am using xilinx web pack verilog design (not schematic design) i instantiate counter in main sending it clk only. inside counter i have always @(posedge clk) counter <= counter + 1; in main, i... also have the same clk. what i am looking to do is have the output of counter go into the input of main. i tried wire, assign and a bunch of other stuff. this is what i ...

Win2kSP4, Apache-2.0.49 + Tomcat-5.0.27 + mod_jk2-2.0.43
OS: Windows 2000, Service Pack 4 Apache ver.: 2.0.49 Tomcat ver.: 5.0.27 mod_jk2 ver.: 2.0.43 We have a server set up to forward requests through Apache to Tomcat using mod_jk2. The setup works, except that periodically it will throw an error as follows on the server: - Application popup: Apache.exe - Application Error : The instruction at "0x6eec7826" referenced memory at "0x00000000". The memory could not be "read". - On the user end, the web app is not interrupted when this happens. In the mod_jk2 error log, the following lines appear when ...

Error while compiling apache 2.2.2
Hi, I got the followinf message while tying to compile apache 2.2.2 under AIX 4.3 with GCC 3. The configure options are : ../configure --prefix=/opt/httpd2 --with-apr=/opt/httpd2/apr --with-apr-util=/opt/httpd2/apr --enable-module="ssl auth_basic auth_digest vhost_alias" --enable-cgi --enable-vhost-alias --enable-ssl --with-ssl=/usr/openssl --enable-http --enable-rewrite --enable-so --with-egd --with-devrand --with-z=/opt/zlib and any try I make I got the only one error message : <snip> /opt/httpd2/apr/build-1/libtool --silent --mode=compile gcc -g -O2 -pthread -U__STR__ -...

Apache 2.2.2 mod_ssl error
I'm trying to migrate from Apache httpd 2.0.46 to 2.2.2. I've managed to sort out most of the configuration, and the http side all seems to be working just fine. However, whenever I try & start the server with the default SSL configuration, and the certificate & key files copied from my previous 2.0.46 installation, the server refuses to start at all, and the log says: [error] Init: Multiple RSA server certificates not allowed What does this mean? Can't find anything by searching Google. Anyone come across this error before? Cheers, -Chrisl Chri...

Error on loading the module #2
hi I compiled the device driver program bfin_adv7393fb.c and the .ko and .o files are generated.after that while loading the module using insmod "bfin_adv7393fb.ko" it gives the following errors::::::: insmod: error inserting "bfin_adv7393fb.ko"-1 invalid module format help me to solve this........ yeah <thiyagu.in@gmail.com> wrote: > insmod: error inserting "bfin_adv7393fb.ko"-1 invalid module format > > help me to solve this........ In your previous posts you have gotten some replies with suggestions of what can be wrong (module compiled for...

2 Module cross dependency
Hi all. I have 2 modules that both needs information from each other. One of them is a network driver(A) and the other(B) is a a module that should interact with the driver. Lets explain how I do so: I set in the driver a timer whose function executes a inter_module_get(B). In B I have a dev_get_by_name in which I use the name of the interface created by the driver. insmod driver.o insmod module.o Then I have a dependency between both modules. The problem arises when I want to rmmod, cause either the resource is busy or the module is busy. Any idea of solv...

import error between 2 modules
I am new to python,and am learning from the tutorials i created 2 .py files like below and put the main in one of them empmodule.py ---------- from workmodule import Worker class Employer: def __init__(self,n): self.name=n self.worker=Worker() def getemployerName(self): return self.name def callWorker(self,message): self.worker.answerCall(message) if __name__ == "__main__": emp=Employer() emp.callWorker("report to work") workmodule.py ------------------ from empmodule import Employer class Worker: def __init__(self...

cross-module reference
Hello All Can one "assign" to a wire in another, instantiated module? Or is a wire not a valid cross-module reference? assign reg_1 = module1.wire1; I'm getting cross-module reference errors in DC and I'm not sure why. Thanks, JB PS: This is difficult to search for, all I get are system verilog hits... -- ----------------------------------------------- John Bleichert syborg@earthlink.net The heat from below can burn your eyes out!! On Mar 4, 1:03=A0pm, John Bleichert <syb...@earthlink.net> wrote: > Hello All > > Can ...

Error in Verilog Code #2
I am new to verilog HDL. I have written code for one algorithm. While simulating, it is giving some errors. Could any body tell how to remove this error The code is as shown in below. module two_pt_FFT(YR,YI,XR,XI ); output reg [31:0] YR [0:1]; output reg [31:0] YI [0:1]; input [31:0] XR [0:1]; input [31:0] XI [0:1]; always @(XR or XI) begin YR[0] = XR[0]+XR[1]; YI[0] = XI[0]+XI[1]; YR[1] = (XR[0]-XR[1]); YI[1] = (XI[0]-XI[1]); end endmodule The test bench program is as shown below module two_pt_fft_dif_tbw; // Inputs wire YR; wire YI; reg [31:0] XR; reg [31:0] XI; // Instan...

[2.5.2] MinGW3.2 W2K lots of linking errors #2
hello, meanwhile I managed to reduce the linking errors: The multiple definitions of `vtable for ...' and the undefined references to `_Unwind_Resume' disapeared when I reduced my potpourri of different gcc-versions. But there are still 530 linking errors, most of them undefined references to `_GLOBAL__D_...', some are undefined references to `SQL...' and a few undefined reference to `wxVariant::...'. Tried to compile a sample, and it's nearly the same, so there is definitly something wrong with the wx-libaries I made by this: mingw32-make -f ...

Getting an error: Attempted to access u(2); index out of bounds because numel(u)=1. Error in ==> treat at 31 if (u(2)>1000) #2
HI, I am using an ode function having three differntial equations in u(1), u(2), (3) using function f=treat(t, u), Now when i use if function as if (u(2)>1000) c=1; else (u(1)<=100) c=0; end i am getting the following error Attempted to access u(2); index out of bounds because numel(u)=1. Error in ==> treat at 31 if (u(2)>1000) Please tell me. thanks "gati " <gatimishrano@yahoo.com> wrote in message news:kfdpbl$ke1$1@newscl01ah.mathworks.com... > HI, I am using an ode function having three differntial equations in u(1), > u(2), (3) using function ...

Re: [2.5.2] MinGW3.2 W2K lots of linking errors #2
hi, got it!! if anybody did the same stupid errors, here the solution: picked out the linking params of a sample and used it: -mthreads -Wl,--subsystem,windows -mwindows -lwxbase25d_odbc -lwxmsw25d_core -lwxbase25d -lwxtiffd -lwxjpegd -lwxpngd -lwxzlibd -lwxregexd -lwxexpatd -lkernel32 -luser32 -lgdi32 -lcomdlg32 -lwinspool -lwinmm -lshell32 -lcomctl32 -lole32 -loleaut32 -luuid -lrpcrt4 -ladvapi32 -lwsock32 -lodbc32 the only thing I don't understand, is the order of the wx-stat.libs. as I undestood the describtion in http://www.wxwid...