Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Could someone please enlighten me?
Thanks,
Malik

laserbeak43 wrote:
> Hello,
>     I've just been shown Signaltap, A feature in Quartus Webpack
> Edition. Does the Webpack Edition of ISE have this feature? WOW this
> alone can convince me to use Altera products.
> 
> Could someone please enlighten me?
> Thanks,
> Malik

There's a feature comparison of different editions of Xilinx here:

http://www.xilinx.com/publications/matrix/Software_matrix.pdf

I believe the equivalent Xilinx feature is ChipScope,

regards
Alan

-- 
Alan Fitch
Doulos
http://www.doulos.com

laserbeak43 <laserbeak43@gmail.com> writes:

> Hello,
>     I've just been shown Signaltap, A feature in Quartus Webpack
> Edition. Does the Webpack Edition of ISE have this feature? WOW this
> alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

On Dec 7, 6:26=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> laserbeak43 <laserbea...@gmail.com> writes:
> > Hello,
> > =A0 =A0 I've just been shown Signaltap, A feature in Quartus Webpack
> > Edition. Does the Webpack Edition of ISE have this feature? WOW this
> > alone can convince me to use Altera products.
>
> Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
> think that's a mistake on Xilinx's part)
>
> But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
> very disjointed and unintegrated in comparison. =A0I'm still using FPGA
> editor to change which signals to monitor, then having to update the
> viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

Use the ChipScope Core Inserter. All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.
From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

-a

Andy Peters <google@latke.net> writes:

> On Dec 7, 6:26�am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>> laserbeak43 <laserbea...@gmail.com> writes:
>> > Hello,
>> > � � I've just been shown Signaltap, A feature in Quartus Webpack
>> > Edition. Does the Webpack Edition of ISE have this feature? WOW this
>> > alone can convince me to use Altera products.
>>
>> Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
>> think that's a mistake on Xilinx's part)
>>
>> But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
>> very disjointed and unintegrated in comparison. �I'm still using FPGA
>> editor to change which signals to monitor, then having to update the
>> viewer by hand! V. tedious.
>
> Really? What version of ChipScope are you using?

10.1.3

>
> Use the ChipScope Core Inserter. 

Indeed, I could (and have in the past), but 

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me 

b) I then have to run MAP, PAR, bitgen again.

> All of the signals and elements of
> the design are shown in it, and you simply choose the signals to
> monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

> From the ChipScope viewer, you can reconfigure the FPGA, then do an
> "Import" which lets you bring in the names of all of the signals you
> selected from the ChipScope Core Inserter project file.
>
> No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious :)

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

interesting. I'll try a chipscope demo...

Thanks

On Dec 9, 6:48=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> Andy Peters <goo...@latke.net> writes:
> > On Dec 7, 6:26=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> >> laserbeak43 <laserbea...@gmail.com> writes:
> >> > Hello,
> >> > =A0 =A0 I've just been shownSignaltap, A feature inQuartusWebpack
> >> > Edition. Does the Webpack Edition of ISE have this feature? WOW this
> >> > alone can convince me to use Altera products.
>
> >> Chipscope is theXilinxequivalent - it's not in webpack (personally, I
> >> think that's a mistake onXilinx'spart)
>
> >> But comparing it toSignaltapmay (IMHO) leave you underwhelmed... it's
> >> very disjointed and unintegrated in comparison. =A0I'm still using FPG=
A
> >> editor to change which signals to monitor, then having to update the
> >> viewer by hand! V. tedious.
>
> > Really? Whatversionof ChipScope are you using?
>
> 10.1.3
>
>
>
> > Use the ChipScope Core Inserter.
>
> Indeed, I could (and have in the past), but
>
> a) I'm using the EDK variety of core inserter, as it manages the JTAG
> linkages with the microblaze debug module for me
>
> b) I then have to run MAP, PAR, bitgen again.
>
> > All of the signals and elements of
> > the design are shown in it, and you simply choose the signals to
> > monitor. After you close the Inserter, go back to ISE, and re-fit.
>
> Re-fit - 10s of minutes.
>
> > From the ChipScope viewer, you can reconfigure the FPGA, then do an
> > "Import" which lets you bring in the names of all of the signals you
> > selected from the ChipScope Core Inserter project file.
>
> > No need to go into the FPGA editor at all!
>
> FPGAeditor, regenerate bitstream, 10s of seconds... =A0Then click "write
> CDC" button, import the result into the analyser. =A0Still tedious :)
>
> As I recall my experience withSignalTap(which was a while ago
> admittedly) I could select a signal from a dropdown list *in the
> Analyser* and it would do the tedious hacking that I currently do in
> FPGAed, regen the bitstream and upload it for me.
>
> Under some circumstances, it would redo a fit at that point, which was
> irritating, but at least I was able to do it all from the analyzer GUI,
> which was then always in sync with the FPGA.
>
> [Followups set to comp.arch.fpga, as it's not very Veriloggy]
>
> Cheers,
> Martin
>
> Crosspost & Followup-To: comp.arch.fpga
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w=
ww.conekt.net/electronics.html

I can't even get this simple code to work in the inserter

module two_input_xor (
	input wire in1,
	input wire in2,
	output wire out
	);
	assign out =3D in1 ^ in2;
endmodule


On Dec 9, 6:48=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> Andy Peters <goo...@latke.net> writes:
> > On Dec 7, 6:26=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> >> laserbeak43 <laserbea...@gmail.com> writes:
> >> > Hello,
> >> > =A0 =A0 I've just been shown Signaltap, A feature in Quartus Webpack
> >> > Edition. Does the Webpack Edition of ISE have this feature? WOW this
> >> > alone can convince me to use Altera products.
>
> >> Chipscope is the Xilinx equivalent - it's not in webpack (personally, =
I
> >> think that's a mistake on Xilinx's part)
>
> >> But comparing it to Signaltap may (IMHO) leave you underwhelmed... it'=
s
> >> very disjointed and unintegrated in comparison. =A0I'm still using FPG=
A
> >> editor to change which signals to monitor, then having to update the
> >> viewer by hand! V. tedious.
>
> > Really? What version of ChipScope are you using?
>
> 10.1.3
>
>
>
> > Use the ChipScope Core Inserter.
>
> Indeed, I could (and have in the past), but
>
> a) I'm using the EDK variety of core inserter, as it manages the JTAG
> linkages with the microblaze debug module for me
>
> b) I then have to run MAP, PAR, bitgen again.
>
> > All of the signals and elements of
> > the design are shown in it, and you simply choose the signals to
> > monitor. After you close the Inserter, go back to ISE, and re-fit.
>
> Re-fit - 10s of minutes.
>
> > From the ChipScope viewer, you can reconfigure the FPGA, then do an
> > "Import" which lets you bring in the names of all of the signals you
> > selected from the ChipScope Core Inserter project file.
>
> > No need to go into the FPGA editor at all!
>
> FPGAeditor, regenerate bitstream, 10s of seconds... =A0Then click "write
> CDC" button, import the result into the analyser. =A0Still tedious :)
>
> As I recall my experience with SignalTap (which was a while ago
> admittedly) I could select a signal from a dropdown list *in the
> Analyser* and it would do the tedious hacking that I currently do in
> FPGAed, regen the bitstream and upload it for me.
>
> Under some circumstances, it would redo a fit at that point, which was
> irritating, but at least I was able to do it all from the analyzer GUI,
> which was then always in sync with the FPGA.
>
> [Followups set to comp.arch.fpga, as it's not very Veriloggy]
>
> Cheers,
> Martin
>
> Crosspost & Followup-To: comp.arch.fpga
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w=
ww.conekt.net/electronics.html

On Dec 13, 3:20=A0pm, laserbeak43 <laserbea...@gmail.com> wrote:
> I can't even get this simple code to work in the inserter
>
> module two_input_xor (
> =A0 =A0 =A0 =A0 input wire in1,
> =A0 =A0 =A0 =A0 input wire in2,
> =A0 =A0 =A0 =A0 output wire out
> =A0 =A0 =A0 =A0 );
> =A0 =A0 =A0 =A0 assign out =3D in1 ^ in2;
> endmodule
>
> On Dec 9, 6:48=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
>
>
> > Andy Peters <goo...@latke.net> writes:
> > > On Dec 7, 6:26=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrot=
e:
> > >> laserbeak43 <laserbea...@gmail.com> writes:
> > >> > Hello,
> > >> > =A0 =A0 I've just been shown Signaltap, A feature in Quartus Webpa=
ck
> > >> > Edition. Does the Webpack Edition of ISE have this feature? WOW th=
is
> > >> > alone can convince me to use Altera products.
>
> > >> Chipscope is the Xilinx equivalent - it's not in webpack (personally=
, I
> > >> think that's a mistake on Xilinx's part)
>
> > >> But comparing it to Signaltap may (IMHO) leave you underwhelmed... i=
t's
> > >> very disjointed and unintegrated in comparison. =A0I'm still using F=
PGA
> > >> editor to change which signals to monitor, then having to update the
> > >> viewer by hand! V. tedious.
>
> > > Really? What version of ChipScope are you using?
>
> > 10.1.3
>
> > > Use the ChipScope Core Inserter.
>
> > Indeed, I could (and have in the past), but
>
> > a) I'm using the EDK variety of core inserter, as it manages the JTAG
> > linkages with the microblaze debug module for me
>
> > b) I then have to run MAP, PAR, bitgen again.
>
> > > All of the signals and elements of
> > > the design are shown in it, and you simply choose the signals to
> > > monitor. After you close the Inserter, go back to ISE, and re-fit.
>
> > Re-fit - 10s of minutes.
>
> > > From the ChipScope viewer, you can reconfigure the FPGA, then do an
> > > "Import" which lets you bring in the names of all of the signals you
> > > selected from the ChipScope Core Inserter project file.
>
> > > No need to go into the FPGA editor at all!
>
> > FPGAeditor, regenerate bitstream, 10s of seconds... =A0Then click "writ=
e
> > CDC" button, import the result into the analyser. =A0Still tedious :)
>
> > As I recall my experience with SignalTap (which was a while ago
> > admittedly) I could select a signal from a dropdown list *in the
> > Analyser* and it would do the tedious hacking that I currently do in
> > FPGAed, regen the bitstream and upload it for me.
>
> > Under some circumstances, it would redo a fit at that point, which was
> > irritating, but at least I was able to do it all from the analyzer GUI,
> > which was then always in sync with the FPGA.
>
> > [Followups set to comp.arch.fpga, as it's not very Veriloggy]
>
> > Cheers,
> > Martin
>
> > Crosspost & Followup-To: comp.arch.fpga
> > --
> > martin.j.thomp...@trw.com
> > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/=
/www.conekt.net/electronics.html- Hide quoted text -
>
> - Show quoted text -

You didn't say what failed, but let me guess what they were.

1) Your simple code above doesn't have a clock so either nothing was
captured or it failed to insert because you didn't define a clock.

2) You tried to use the nets in1, in2 and out as the TRIGGER and DATA
sources and this failed.  These net names become the PADs in the
design and can not be probed. You need to use the net attached to the
IBUF output for "in1" and "in2" and the net attached to the OBUF input
for "out".

This code would be a better simple design, using clock, in1_reg,
in2_reg and xor_reg.

odule two_input_xor (
        input  wire in1,
        input  wire in2,
        input  wire clock,
        output reg out
        );

reg in1_reg, in2_reg, xor_reg;

// Input Registers
always @ (posedge clock) begin
   in1_reg <=3D in1;
   in2_reg <=3D in2;
end

// Internal Registers
always @ (posedge clock) begin
   xor_reg <=3D in1_reg ^ in2_reg;
end

// Output Registers
always @ (posedge clock) begin
   out <=3D xor_reg;
end

endmodule