Creating delay chain with genericsttobsen 5 2 Hi I try to implement a synthesizable delay chain. Here a working example: library ieee; use ieee.std_logic_1164.all; entity delay_gate is ge...
VHDL automate help, beginnerhehehmhm 17 2 Hey I'm having some problems with my code lock machine. It is for simulation. Here is my code: http://www.box.com/s/129cbfc83b936f275292 It is a lo...
State machine with D Flip Flopwouter3882 6 1 Hi list, For education purposes I am building a state machine. I made the state tables, simplification with karnaugh maps, state table for the output...
Ideas on higher level designvtxsupport 4 2 Hi, Pleased to introduce my new tool, VTM 2012. It is intended to be a table based edit tool for Verilog/VHDL module's interface definition, and unify...
Parametrized CLA adder in VHDLbojanjov 3 1 Hi there, I need to implement Carry Look Ahead binary Adder in FPGA, by describing it in a parametrized way. I want to use the following approach: 1...
Problems switching to ieee.numeric_std.allaleksaZR 14 4 My VHD files now begin with library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; and I have some questions... Example1: I'm copy...
Counter with asynchronous enableramya.murali.d 3 1 I have a counter (positive edge triggered) whose enable (active high) is generated by a two state FSM (positive edge state transition). Counter_enable...