Is there a standard library function (e.g., to_real) to convert a std_logic_vector to a real value? If not, how would one go about doing this?

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8/4/2005 8:15:58 PM

eNo wrote: > Is there a standard library function (e.g., to_real) to convert a > std_logic_vector to a real value? If not, how would one go about doing this? With IEEE.numeric_std.all signal slv : std_logic_vector(bitwidth-1 downto 0); signal sru,srs : real; sru<=to_real(to_integer(unsigned(slv))); -- or srs<=to_real(to_integer(signed(slv))); It looks not nice with IEEE.numeric_std, but as noted the decision for signed / unsigned is nessecary and therefore IEEE.numeric_std is recommended. Ralf

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8/5/2005 5:54:22 PM

The problem lies in the fact that you can represent real values in different ways as bits. The IEEE floating point format defines a standard doing this for single/double precision. First converting to a signed or unsigned integer does not solve the problem in all cases. I do not know of any standard library functions to convert std_logic_vector representations of IEEE floating point to real. As the term "floating point" suggests, the decimal point floats. An part of the format (exponent) defines the position of the decimal point here. In hardware, often fixed point arithmetic will do. You could use 24 bits before and 8 bits after the decimal point. In this case, convert to integer, divide by 2**8 and assign to the real value. Integer aithmetic in VHDL is restricted to the range integer'low to integer'high, which is only guaranteed to work for vectors up to 32 bits, so first converting to integer and then to real may not work for larger vectors Hubble.

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8/9/2005 6:02:02 PM

Hi , please my problem is how to use real constant for example 0.1913 and multiply it with an std_logic_vector(7 downto 0) and as an exmple to remplace reals b std_logic_vector , i did find that -- Y = 0.299 * R.000 + 0.587 * G.000 + 0.114 * B.000 -- Y = 0x132 * R + 0x259 * G + 0x074 * B -- -- Cr = 0.713(R - Y) -- Cr = 0.500 * R.000 + -0.419 * G.000 - 0.0813 * B.000 -- Cr = (R >> 1) - 0x1AD * G - 0x053 * B -- Cb = 0.565(B - Y) -- Cb = -0.169 * R.000 + -0.332 * G.000 + 0.500 * B.000 -- Cb = (B >> 1) - 0x0AD * R - 0x153 * G please i cant get how the reals are converted...

hello friends i found one fatal error , when i multiply two signals ie., one signal is being real type and another one is integer type.. coding below entity < > port ( w : in real;n : integer; result : out real); end < > architecture < > of < > is signal tmp : real; begin tmp <= real(n); result <= w*tmp; end <>; after i force values to w i found on the screen Fatal: Value -Inf is out of range -1e+308 to 1e+308 Fatal error at /export/home/mvs/mvs014/senthil/Sem3/sample.vhd line 9 ie., at result <= n * tmp; please give some ideas... thank u expec...

i'm a beginner in vhdl. please tell me how to convert real type to std_logic_vector ? i wrote as: process variable input_line : line; variable input_data : real; begin i <= 0; xn_re <= "0000000000000000"; while not endfile(DATA_FILE) loop readline(DATA_FILE, input_line); read(input_line, input_data); xn_re <= std_logic_vector(to_signed(integer(input_data), 16));-----here is the problem,but if i use xn_re <= conv_std_logic_vector(input_data, 16); the input_data should not be a real type....., then i don't know how to ...

Hi I Have 2 constant values nu= 3.131764231e-3 and v = 0.993736471 Later on in my VHDL code I have to multiply these with two values which are std_logic_vectors of 20bits. So I would like to convert these constants to vectors of 20 bits without losing precision.How could I do so in VHDL tried to do conv_std_logic_vector(nu,20); unfortunately it didnt work! Please if anyone could help me I would be grateful Thanks Sudsy "Sudhir" <sudsyrao@gmail.com> wrote in message news:1170497955.156964.126610@v45g2000cwv.googlegroups.com... > Hi > > I Have 2 constant values...

Hello everyone, I am trying to divite a std_logic_vector by a std_logic_vector. So i converted both of them into integers and divided. But how do i convert back to std_logic_vector. 1) Is the integer type or the division" / " synthesizable in xilinx ISE. 2) if i use integer as my output port and when i download my code onto the fpga, does it convert back to the binary. If yes to how many bits. I appreciate if you could answer these questions thanks Ashwin ashwin wrote: > Hello everyone, > I am trying to divite a std_logic_vector by a std_logic_vector. > So i conv...

Hi, Does anyone know how I can convert my verilog code to VHDL? Stanley liying.chang@verizon.net wrote: > Hi, > Does anyone know how I can convert my verilog code to VHDL? Have a look at http://www.eda.org/comp.lang.vhdl/FAQ3.html#verilog2vhdl Paul. ...

Hi If anyone has vhdl2verilog converter script please post it to me. or please let me know what is wrong with the below code. i have one but it is showing some syntax erros at , but simulator did not show any error. entity mst_wrap is generic ( --synopsys translate_off dump_file: in string:= "mst_wrap.log"; // syntax error it is showing ???? i dont know vhdl. dump_type: in integer:= dump_no; --synopsys translate_on ahb_max_addr: in integer:= 4; entity ahb_slave_wait is generic ( num_slv: in integer range 0 to 15:= 1; // syntax error here also. fifohempty_level: in in...

Hi, Does anyone know how I can convert my verilog code to VHDL? Stanley <liying.chang@verizon.net> wrote in message news:<yWYob.63946$1C5.22696@nwrdny02.gnilink.net>... > Hi, > Does anyone know how I can convert my verilog code to VHDL? Ummm, by hand? -a by hand :) another way is using EDA tools likes Visual HDL and HDL Designer's Serise. (and synthesis tools can export vhdl netlist from verilog RTL) <liying.chang@verizon.net> wrote in message news:yWYob.63946$1C5.22696@nwrdny02.gnilink.net... > Hi, > Does anyone know how I can convert my verilog code to VHDL? > > Stanley > > The main question is: do we want conversion on RTL or Gate levels? For RTL, I completely agree that "by hand" approach is the safest one. For gatelevel, just dump your design to vhdl format after running synthesis, or load your verilog gatelevel to the synthesis tool and then save it in vhdl format. Regards, Alexander "Kim Hyun-Gyu" <babyworm@adc.co.kr.NOSPAM> wrote in message news:<bo73sp$khq$1@news.elim.net>... > by hand :) > another way is using EDA tools likes Visual HDL and HDL Designer's Serise. > (and synthesis tools can export vhdl netlist from verilog RTL) > > > <liying.chang@verizon.net> wrote in message > news:yWYob.63946$1C5.22696@nwrdny02.gnilink.net... > > Hi, > > Does anyone know how I can convert my verilog c...

Hi guys, I've got a problem with ToExpression[]. It seems to round large real numbers off, e.g. ToExpression["109266.75"] returns 109267., still a real, yet not exactly what the original string meant. Any idea to solve this? Many thanks fcaleyo ...

I need to convert a std_logic_vector into an unsigned, and I am surprised that this seems not to work. signal a : std_logic_vector ( 5 downto 0 ); signal b : unsigned ( 5 downto 0 ); I tried: b <= a; b <= to_unsigned ( a, 6 ); b <= conv_unsigned ( a, 6 ); with used libs (several combinations commented in or out): library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --do not use both ??? --use ieee.numeric_bit.all; use ieee.numeric_std.all; --use ieee.std_logic_unsigned.all; all with Xilinx web pack 6.2.03i. Syntax check claims in different ways, usually ...ca...

Hi all, Can any one inform me the various steps needed to convert a C coding in to VHDL. Please tell the list of Websites that gives information regarding this topic. Thanks in Advance, Sarath sarath1111@gmail.com wrote: > Can any one inform me the various steps needed to convert a C coding > in to VHDL. Please tell the list of Websites that gives information > regarding this topic. IMHO... 1. Understand what the C code is trying to achieve, and what algorithms are used to achieve that. 2. Think about how that same problem might be solved in hardware consisting of memories...

Hi, This isnt a very "code" oriented question, but Im developing a code to simulate a body travelling under a central force. The units for distance I am using are in A.U for convenience, but Im trying to convert the time over which the simulation takes place back into real time for presentation sake. So say for example I have: z=[x_position; y_position; x_velocity; y_velocity] Time=zeros(1110,1) %create zero vector to hold the times tend=0.1 for i=1:100 [t,z]=ode45(@twobodyfunctionmars,[0:0.01:tend],z0,options); Time(1:length(z))=t(:,1); end now, Ive used: Time_total=l...

Hi all, do you know any good program that converts VHDL to Verilog ?! thanks in advance -Amir "Amir" <sting.t2@gmail.com> wrote in message news:1188975738.872743.148600@w3g2000hsg.googlegroups.com... > Hi all, > > do you know any good program that converts VHDL to Verilog ?! > Personally I wouldn't go down this route but you can try XHDL (http://www.ids4eda.com/xhdl.htm), you might have to do some manual editing before converting. Why are you trying to do this? Hans www.ht-lab.com > thanks in advance > -Amir > thanks, well I am working on a Verilog Project, and received from my partner a module in VHDL, I want to integrate it to the Project. by the way , found a free one , I don't know if you know it http://www.ocean-logic.com/downloads.htm -Amir Amir wrote: > well I am working on a Verilog Project, and received from my partner a > module in VHDL, I want to integrate it to the Project. Just intergate the VHDL code directly inside the verilog. All the real tools nowadays support mixed mode functionality (simulation, synthesis etc.) --Kim "Amir" <sting.t2@gmail.com> wrote in message news:1188982229.702139.141850@22g2000hsm.googlegroups.com... > thanks, > > well I am working on a Verilog Project, and received from my partner a > module in VHDL, I want to integrate it to the Project. > > by the way , found a free o...

Hello everyone. I had a code for fixed point division by Verilog. I tried to rewrite it with VHDL but not successfull. Can somebody help me? Thanks so much. module division #( //Parameterized values parameter Q = 4, // number of fraction bits parameter N = 8 ) ( input [N-1:0] i_dividend, input [N-1:0] i_divisor, input i_start, input i_clk, output [N-1:0] o_quotient_out, output o_complete, output o_overflow ); reg [2*N+Q-3:0] reg_working_quotient;// Our working copy of the quotient reg [N-1:0] reg_quotient; // Final quotient reg [N-2+Q:0] reg_w...

I would like to know how I can convert rationals into reals with four digits. I know this sounds stange but I need the numbers for a diagram. If anyone knows how to covert a whole list of rationals into into four digit reals I would be very happy. Thank you very much for help. Kristoph kristoph schrieb: > I would like to know how I can convert rationals into reals with four > digits. I know this sounds stange but I need the numbers for a diagram. > > If anyone knows how to covert a whole list of rationals into into four > digit reals I would be very happy. &g...

I am about to start rewriting a fortran program to ansi C++. Would it be best to convert the variables that are 'real' to float? double? long double? Al wrote: > I am about to start rewriting a fortran program to ansi C++. Step 1: use f2c, to translate Fortran source into complete C source that compiles and runs. F2C is so stable that many use it as their Fortran compiler. They never read the C intermediate. Step 2: Read the C intermediate. It is not that bad, once you learn how stereotypically it wraps all the Fortran nuances. But it won't be C++. Don't ask it to be a...

hi, i have project in ahdl (max plus II). Is it possible to convert it to vhdl? I tried to use XPort, but there were errors. zlotawy On Jan 30, 12:07 pm, "zlotawy" <spaw...@NNOOSSPPAAMM.wp.pl> wrote: > hi, > i have project in ahdl (max plus II). Is it possible to convert it to vhdl? > > I tried to use XPort, but there were errors. > > zlotawy Xilinx has an ahdl to vhdl translator, but the license is limited to use with xilinx fpga's. Call Altera and tell them you're going to switch devices if they don't translate it for you, or start provid...

I know there have been so many posts on this topic. But for some reason my code doesnt work and i dont see anything wrong with it. I read through most posts and i dont seem to be doing any different from whats being suggested... I am using th xilinx webpack.... the code is below.. i get an error saying that i cannot use operands in TO_INTEGER in this context.... I can figure out whats wrong... Thanks in advance guys, Sai ------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.ALL; entity intege...

I have a problem converting an enum with known encoding to a std_logic_vector. Here's some fragments of the code: entity controller is port ( ... ledsel : out std_logic_vector(1 downto 0); ... ); ctrl_proc : process(clock) type opmode_t is (OPMODE_IDENT, OPMODE_CONFIG, OPMODE_ACQ); attribute enum_encoding : string; attribute enum_encoding of opmode_t : type is "00 01 10"; variable opmode_v : opmode_t; I now want to assign opmode_v to the ledsel output and thought to do it like this: ledsel <= std_logic_vector(opmode_v);...

I have a JED file for an old PAL device and I have to put this design in a FPGA. Is there a tool that can read the JED file and translate it to any usable language (VHDL prefered)... On 8 Nov 2006 23:15:29 -0800, lingamaneni.naveen@gmail.com wrote: >I have a JED file for an old PAL device and I have to put this design >in a FPGA. JED != ABEL. You have only the fusemap! >Is there a tool that can read the JED file and translate it to any >usable language (VHDL prefered)... Yup. It's a sloppy bag of fats and proteins suspended in salty water, and it sits between your ears....

Hi all, I'm looking for a tool for converting VHDL entity information (ports, generics) into XML, so I can integrate it in A Docbook document easily. It seem that Quartus and Modelsim can do this (though undocumented in Quartus), but I'm looking for a hardware design tool independent way for doing this, most prefferably open source. If anyone knows about a tool for automatic documentation (like Doxygen for C) I would love to hear about. I know vhdldoc, but it only makes HTML, and I really need XML. Thanks, Avishay "avishay" <avishorp@yahoo.com> writes: > I'm ...

Hello group, I have been updating some of my code and started using records to try to organize and parameterize the code. Specifically I have a record type, signals, and arrays like this: package blobleft_package is type f1_type is record left_edge : std_logic_vector(11 downto 0); left_orig : std_logic_vector(11 downto 0); done : std_logic; height : std_logic_vector(8 downto 0); age : std_logic_vector(8 downto 0); end record; end blobleft_package; I like the way this has improved my code, and the way the sigs look in ModelSim, except for the problem when I need to co...

hello all, any idea how can i convert matlab file into vhdl file without using hdl coder?? if hdl coder is the only way.. could you plz me help me how can i use it... thanks, Niveen. "Niveen Morsi" <niveen_morsi@hotmail.com> wrote in message news:khn52v$4qv$1@newscl01ah.mathworks.com... > hello all, > > any idea how can i convert matlab file into vhdl file without using hdl > coder?? Manual conversion? > if hdl coder is the only way.. could you plz me help me how can i use > it... The Getting Started section of the documentati...

Hi, Does anyone know how I can convert my verilog code to VHDL? Stanley <sc01@hotmail.com> wrote in message news:5vFob.60444$1C5.41226@nwrdny02.gnilink.net... > Hi, > Does anyone know how I can convert my verilog code to VHDL? I would ask in comp.lang.verilog or comp.lang.vhdl -- glen Do not forget to mention level of description (RTL or structural). The latter should be simpler. X-HDL: http://www.x-tekcorp.com/xhdl3.htm The demo doesn't allow you to save it, though. <sc01@hotmail.com> wrote: :Hi, :Does anyone know how I can convert my verilog code to VHDL?...

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