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entity component binding issue with configurations

I have binding warnings http://paste2.org/La9jIxbF with http://paste2.org/wnHDY0g3   How do I solve them ?   even I modify the configuration as in http://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32 
0
Marvin
10/23/2016 7:17:56 AM
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On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote:
> I have binding warnings http://paste2.org/La9jIxbF with http://paste2.org=
/wnHDY0g3   How do I solve them ?   even I modify the configuration as in h=
ttp://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32

I have solved the binding compilation warning.=20

Now, I could not view the internal signal http://i.imgur.com/w4jwnN1.png ev=
en though I am using the formal format *ghw with http://paste2.org/mVMOJZYA=
 , http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , http://paste2.=
org/FDh4c6Av and http://paste2.org/UwgnBnds
0
Marvin
10/24/2016 1:59:32 AM
On 10/23/2016 9:59 PM, Marvin L wrote:
> On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote:
>> I have binding warnings http://paste2.org/La9jIxbF with
>> http://paste2.org/wnHDY0g3   How do I solve them ?   even I modify
>> the configuration as in http://paste2.org/bJZJPdWt , I have this
>> error http://paste2.org/BLW1yg32
>
> I have solved the binding compilation warning.
>
> Now, I could not view the internal signal
> http://i.imgur.com/w4jwnN1.png even though I am using the formal
> format *ghw with http://paste2.org/mVMOJZYA ,
> http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 ,
> http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds

Hi Marvin,

I don't know how to help you.  I'm not at all familiar with the tools 
you are using.  I know I don't have this problem with Aldec Active-HDL.

Can you explain the problem you had initially and how you fixed it? 
Others may have the same problem in the future.  Likewise, when you fix 
this problem please post what you found.

-- 

Rick C
0
rickman
10/24/2016 11:42:08 PM
On Tuesday, October 25, 2016 at 7:42:09 AM UTC+8, rickman wrote:
> On 10/23/2016 9:59 PM, Marvin L wrote:
> > On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote:
> >> I have binding warnings http://paste2.org/La9jIxbF with
> >> http://paste2.org/wnHDY0g3   How do I solve them ?   even I modify
> >> the configuration as in http://paste2.org/bJZJPdWt , I have this
> >> error http://paste2.org/BLW1yg32
> >
> > I have solved the binding compilation warning.
> >
> > Now, I could not view the internal signal
> > http://i.imgur.com/w4jwnN1.png even though I am using the formal
> > format *ghw with http://paste2.org/mVMOJZYA ,
> > http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 ,
> > http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds
> 
> Hi Marvin,
> 
> I don't know how to help you.  I'm not at all familiar with the tools 
> you are using.  I know I don't have this problem with Aldec Active-HDL.
> 
> Can you explain the problem you had initially and how you fixed it? 
> Others may have the same problem in the future.  Likewise, when you fix 
> this problem please post what you found.
> 
> -- 
> 
> Rick C

I have solved the previous problem because I have forgotten to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd

what does mutiple architecture means as in http://www.edaboard.com/thread360462.html ? How do I fix that ?

anything wrong with the compile order as in the makefile at http://paste2.org/Kv7vD8xL ?
0
Marvin
10/25/2016 3:50:15 AM
On 10/24/2016 11:50 PM, Marvin L wrote:
> On Tuesday, October 25, 2016 at 7:42:09 AM UTC+8, rickman wrote:
>> On 10/23/2016 9:59 PM, Marvin L wrote:
>>> On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote:
>>>> I have binding warnings http://paste2.org/La9jIxbF with
>>>> http://paste2.org/wnHDY0g3   How do I solve them ?   even I modify
>>>> the configuration as in http://paste2.org/bJZJPdWt , I have this
>>>> error http://paste2.org/BLW1yg32
>>>
>>> I have solved the binding compilation warning.
>>>
>>> Now, I could not view the internal signal
>>> http://i.imgur.com/w4jwnN1.png even though I am using the formal
>>> format *ghw with http://paste2.org/mVMOJZYA ,
>>> http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 ,
>>> http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds
>>
>> Hi Marvin,
>>
>> I don't know how to help you.  I'm not at all familiar with the tools
>> you are using.  I know I don't have this problem with Aldec Active-HDL.
>>
>> Can you explain the problem you had initially and how you fixed it?
>> Others may have the same problem in the future.  Likewise, when you fix
>> this problem please post what you found.
>>
>> --
>>
>> Rick C
>
> I have solved the previous problem because I have forgotten to compile subbytes.vhd and round_constant.vhd together with key_expansion.vhd
>
> what does mutiple architecture means as in http://www.edaboard.com/thread360462.html ? How do I fix that ?
>
> anything wrong with the compile order as in the makefile at http://paste2.org/Kv7vD8xL ?

I can't say if your compile order is good or not without going through 
all the code.  Any module that invokes another module must be compiled 
*after* the invoked module has been compiled.  At least that is how the 
tools I use do it.  They automatically scan the files looking for 
dependencies and order the files appropriately.

I have never run into multiple architectures before, but I suppose it 
means you have more than one architecture with the same name?

-- 

Rick C
0
rickman
10/25/2016 4:38:49 AM
On Tue, 25 Oct 2016 00:38:49 -0400, rickman wrote:

> On 10/24/2016 11:50 PM, Marvin L wrote:
>> On Tuesday, October 25, 2016 at 7:42:09 AM UTC+8, rickman wrote:
>>> On 10/23/2016 9:59 PM, Marvin L wrote:
>>>> On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote:
>>>>> I have binding warnings http://paste2.org/La9jIxbF with
>>>>> http://paste2.org/wnHDY0g3   How do I solve them ?   even I modify
>>>>> the configuration as in http://paste2.org/bJZJPdWt , I have this
>>>>> error http://paste2.org/BLW1yg32
>>>>
>>>> I have solved the binding compilation warning.
>>>>
>>>> Now, I could not view the internal signal
>>>> http://i.imgur.com/w4jwnN1.png even though I am using the formal
>>>> format *ghw with http://paste2.org/mVMOJZYA ,
>>>> http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 ,
>>>> http://paste2.org/FDh4c6Av and http://paste2.org/UwgnBnds
>>>
>>> Hi Marvin,
>>>
>>> I don't know how to help you.  I'm not at all familiar with the tools
>>> you are using.  I know I don't have this problem with Aldec
>>> Active-HDL.
>>>
>>> Can you explain the problem you had initially and how you fixed it?
>>> Others may have the same problem in the future.  Likewise, when you
>>> fix this problem please post what you found.
>>>
>>> --
>>>
>>> Rick C
>>
>> I have solved the previous problem because I have forgotten to compile
>> subbytes.vhd and round_constant.vhd together with key_expansion.vhd
>>
>> what does mutiple architecture means as in
>> http://www.edaboard.com/thread360462.html ? How do I fix that ?
>>
>> anything wrong with the compile order as in the makefile at
>> http://paste2.org/Kv7vD8xL ?
> 
> I can't say if your compile order is good or not without going through
> all the code.  Any module that invokes another module must be compiled
> *after* the invoked module has been compiled.  At least that is how the
> tools I use do it.  They automatically scan the files looking for
> dependencies and order the files appropriately.
> 
> I have never run into multiple architectures before, but I suppose it
> means you have more than one architecture with the same name?


Let's take those things one at a time.

> Any module that invokes another module must be compiled
> *after* the invoked module has been compiled.

That's true if using entity instantiation.  It's not true if using 
component instantiation.  Components merely need to be compiled before 
elaboration.

> At least that is how the
> tools I use do it.  They automatically scan the files looking for
> dependencies and order the files appropriately.

My experience has been that tools that try to guess the compile order 
will violate the LRM if confronted by unusual conditions such as 
configurations or multiple architectures for the one entity.
(BTW, I only really have experience with Xilinx and Altera tools.  Other 
tools may be better or worse.  I'm not hopeful though.)

> I have never run into multiple architectures before, but I suppose it
> means you have more than one architecture with the same name?

It's allowable to have multiple architectures (with unique names) for a 
given entity.  This is commonly done, e.g. for RAM models - you might 
have a (quick to simulate) behavioural one, as well as a (slow to 
simulate) one with accurate timing.

You can select between different architectures in multiple ways.
- You can specify the architecture name in an entity instantiation.
- You can use a configuration.
- If not specified, it will default to the most recently compiled 
architecture.

Regards,
Allan
0
Allan
10/25/2016 10:04:17 AM
On Monday, October 24, 2016 at 2:59:38 PM UTC+13, Marvin L wrote:
> On Sunday, October 23, 2016 at 3:18:01 PM UTC+8, Marvin L wrote:
> > I have binding warnings http://paste2.org/La9jIxbF with http://paste2.o=
rg/wnHDY0g3   How do I solve them ?   even I modify the configuration as in=
 http://paste2.org/bJZJPdWt , I have this error http://paste2.org/BLW1yg32
>=20
> I have solved the binding compilation warning.=20
>=20
> Now, I could not view the internal signal http://i.imgur.com/w4jwnN1.png =
even though I am using the formal format *ghw with http://paste2.org/mVMOJZ=
YA , http://paste2.org/vpbvXcID , http://paste2.org/1pAZac73 , http://paste=
2.org/FDh4c6Av and http://paste2.org/UwgnBnds

Other than an unneeded use clause for package numeric_std in key_expansion.=
vhd the only errors causing 'U's are in round_constant.vhd:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity round_constant is
    port
    (
        CLK    	: in   	std_logic;
	key_load: in   	std_logic;
        rcon: out   std_logic_vector(31 downto 0)
    );
=20
attribute SIGIS : string;
attribute SIGIS of CLK : signal is "Clk";
=20
end round_constant;

architecture EXAMPLE of round_constant is -- WAS key_expansion is

signal rcnt_next, rcnt: integer :=3D 0;
-- signal rcon : std_logic_vector(31 downto 0) :=3D (OTHERS =3D> '0');  -- =
NAME
signal rcon_next : std_logic_vector(31 downto 0) :=3D (OTHERS =3D> '0'); --=
 CHANGED
begin


process(clk)
begin

if rising_edge(clk) then
	if(key_load =3D '1') then=09
		rcon <=3D x"01000000";
		rcnt <=3D 0;
	else
        rcon <=3D rcon_next;  -- ADDED=09
		rcnt <=3D rcnt_next;
	end if;
end if;
end process;

rcnt_next <=3D rcnt + 1;


process(rcnt_next)
begin
=09
	case(rcnt_next) is
       -- when 0 =3D> rcon <=3D x"01_00_00_00";  -- CHANGE rcon to rcon_nex=
t
       -- when 1 =3D> rcon <=3D x"02_00_00_00";
       -- when 2 =3D> rcon <=3D x"04_00_00_00";
       -- when 3 =3D> rcon <=3D x"08_00_00_00";
       -- when 4 =3D> rcon <=3D x"10_00_00_00";
       -- when 5 =3D> rcon <=3D x"20_00_00_00";
       -- when 6 =3D> rcon <=3D x"40_00_00_00";
       -- when 7 =3D> rcon <=3D x"80_00_00_00";
       -- when 8 =3D> rcon <=3D x"1b_00_00_00";
       -- when 9 =3D> rcon <=3D x"36_00_00_00";
       -- when OTHERS =3D> rcon <=3D x"00_00_00_00";
	   when 0 =3D> rcon_next <=3D x"01_00_00_00";
	   when 1 =3D> rcon_next <=3D x"02_00_00_00";
	   when 2 =3D> rcon_next <=3D x"04_00_00_00";
	   when 3 =3D> rcon_next <=3D x"08_00_00_00";
	   when 4 =3D> rcon_next <=3D x"10_00_00_00";
	   when 5 =3D> rcon_next <=3D x"20_00_00_00";
	   when 6 =3D> rcon_next <=3D x"40_00_00_00";
	   when 7 =3D> rcon_next <=3D x"80_00_00_00";
	   when 8 =3D> rcon_next <=3D x"1b_00_00_00";
	   when 9 =3D> rcon_next <=3D x"36_00_00_00";
	   when OTHERS =3D> rcon_next <=3D x"00_00_00_00";
	end case;

end process;

end architecture EXAMPLE;

Notice you had the entity name wrong in the architecture, I converted the a=
rchitecture declarative part signal declaration of rcon to rcon_next, chang=
ed the assignments in the case statement in the process, and added an assig=
nment to rcon from rcon_next in your register process.

0
diogratia
10/25/2016 10:13:15 AM
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