So, lets start learning and programming vhdl with the Xilinx ISE.
I want to simulate a sinus generator. At the moment there is no FPGA
board available.
I must first learn VHDL.
I have generated a package with a table lookup.
Here is the package body.

library ieee;
use ieee.std_logic_1164.all;

package sine_package is

  constant max_table_value: integer :=3D 255;
  subtype table_value_type is integer range 0 to max_table_value;

  constant max_table_index: integer :=3D 255;
  subtype table_index_type is integer range 0 to max_table_index;

  subtype sine_vector_type is std_logic_vector( 8 downto 0 );

  function get_table_value (table_index: table_index_type) return
table_value_type;

end;

Now I want to use the table lookup.
The package has been compiled.

-- SineWaveLoop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- use sine_package.ALL;

entity sine_wave_loop is
   port (do_sine_wave : in bit; output : out
sine_package.table_value_type);
end sine_wave_loop;

architecture behaviour of sine_wave_loop is
begin
	sine_loop : process(do_sine_wave)
		variable counter : sine_package.max_index_type;   <----------- This
is Line 10
	begin
		counter =3D 0;
		while (do_sine_wave =3D '1') loop
			counter =3D (counter + 1) mod sine_package.max_table_index;
			output =3D  sine_package.get_table_value(counter);
		end loop;
	end process sine_loop;
end behaviour;

And thats the error (One of them):

 Line 10. Symbol sine_package can't be used as a prefix in a selected
name.

So, what is the problem ?
Isn=B4t it the correct syntax like <Package_Name>.<Type> ?
You can use the use statement or use the point operator but not both.

HansWernerMarschke@web.de a �crit:
> So, lets start learning and programming vhdl with the Xilinx ISE.
> I want to simulate a sinus generator. At the moment there is no FPGA
> board available.
> I must first learn VHDL.
> I have generated a package with a table lookup.
> Here is the package body.
> 
> library ieee;
> use ieee.std_logic_1164.all;
> 
> package sine_package is
> 
> constant max_table_value: integer := 255;
> subtype table_value_type is integer range 0 to max_table_value;
> 
> constant max_table_index: integer := 255;
> subtype table_index_type is integer range 0 to max_table_index;
> 
> subtype sine_vector_type is std_logic_vector( 8 downto 0 );
> 
> function get_table_value (table_index: table_index_type) return
> table_value_type;
> 
> end;
> 
> variable counter : sine_package.max_index_type;

And where is defined max_index_type in the package? 

Anyway, this solution "compiles": 

library ieee;
use ieee.std_logic_1164.all;

package sine_package is

  constant max_table_value : integer := 255;
  subtype table_value_type is integer range 0 to max_table_value;

  constant max_table_index : integer := 255;
  subtype table_index_type is integer range 0 to max_table_index;

  subtype sine_vector_type is std_logic_vector(8 downto 0);

  function get_table_value (table_index : table_index_type) return
    table_value_type;

end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.sine_package.ALL;

entity sine_wave_loop is
  port (
    do_sine_wave : in bit;
    output : out table_value_type);
end sine_wave_loop;

architecture behaviour of sine_wave_loop is
begin
  sine_loop : process(do_sine_wave)
    variable counter : table_index_type; // Change to table_index_type
  begin
    counter := 0;
    while (do_sine_wave = '1') loop
      counter := (counter + 1) mod max_table_index;
      output <= get_table_value(counter);
    end loop;
  end process sine_loop;
end behaviour;


-- 
Vince

Thanks a lot