how to write SD ram - comp.lang.vhdl

hi this is the top level design of the SDRAM controller, can some one point me out how to read data, process it (for ex: addition, subtraction, etc) and write it back to memory. I know it can be done with the sData signal, but how i don't know. library IEEE; use IEEE.std_logic_1164.all; use WORK.test_board_core_pckg.all; entity test_board is port( ce_n : out std_logic; -- Flash RAM chip-enable sw2 : in std_logic; -- active-low pushbutton input clk : in std_logic; -- main clock input from external clock source sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays sclk : out std_logic; -- clock to SDRAM cke : out std_logic; -- SDRAM clock-enable cs_n : out std_logic; -- SDRAM chip-select ras_n : out std_logic; -- SDRAM RAS cas_n : out std_logic; -- SDRAM CAS we_n : out std_logic; -- SDRAM write-enable ba : out std_logic_vector( 1 downto 0); -- SDRAM bank- address sAddr : out std_logic_vector(12 downto 0); -- SDRAM address bus sData : inout std_logic_vector(15 downto 0); -- data bus to/from SDRAM dqmh : out std_logic; -- SDRAM DQMH dqml : out std_logic; -- SDRAM DQML s : out std_logic_vector(6 downto 0); -- 7-segment LED pps : out std_logic_vector(6 downto 3) -- outputs to parallel port status bits ); end entity; architecture arch of test_board is begin ce_n <= '1'; -- disable Flash RAM u0 : test_board_core generic map( FREQ => 100_000, PIPE_EN => true, DATA_WIDTH => sData'length, SADDR_WIDTH => sAddr'length, NROWS => 8192, NCOLS => 512, BEG_ADDR => 16#00_0000#, END_ADDR => 16#FF_FFFF#, BEG_TEST => 16#00_0000#, END_TEST => 16#FF_FFFF# ) port map( button_n => sw2, clk => clk, sclkfb => sclkfb, sclk => sclk, cke => cke, cs_n => cs_n, ras_n => ras_n, cas_n => cas_n, we_n => we_n, ba => ba, sAddr => sAddr, sData => sData, dqmh => dqmh, dqml => dqml, led => s, heartBeat => pps(6) ); end arch; thanks

On Apr 5, 3:30=A0am, mightycatniyan...@gmail.com wrote: > hi > > this is the top level design of the SDRAM controller, can some one > point me out how to read data, process it (for ex: addition, > subtraction, etc) and write it back to memory. I know it can be done > with the sData signal, but how i don't know. > > library IEEE; > use IEEE.std_logic_1164.all; > use WORK.test_board_core_pckg.all; > > entity test_board is > =A0 port( > =A0 =A0 ce_n =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- Flash RAM ch= ip-enable > =A0 =A0 sw2 =A0 =A0: in =A0 =A0std_logic; =A0 =A0 =A0 =A0 =A0 -- active-l= ow pushbutton input > =A0 =A0 clk =A0 =A0: in =A0 =A0std_logic; =A0 =A0 =A0 =A0 =A0 -- main clo= ck input from > external clock source > =A0 =A0 sclkfb : in =A0 =A0std_logic; =A0 =A0 =A0 =A0 =A0 -- feedback SDR= AM clock with > PCB delays > =A0 =A0 sclk =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- clock to SDR= AM > =A0 =A0 cke =A0 =A0: out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM cloc= k-enable > =A0 =A0 cs_n =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM chip-s= elect > =A0 =A0 ras_n =A0: out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM RAS > =A0 =A0 cas_n =A0: out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM CAS > =A0 =A0 we_n =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM write-= enable > =A0 =A0 ba =A0 =A0 : out =A0 std_logic_vector( 1 downto 0); =A0-- SDRAM b= ank- > address > =A0 =A0 sAddr =A0: out =A0 std_logic_vector(12 downto 0); =A0-- SDRAM add= ress > bus > =A0 =A0 sData =A0: inout std_logic_vector(15 downto 0); =A0-- data bus to= /from > SDRAM > =A0 =A0 dqmh =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM DQMH > =A0 =A0 dqml =A0 : out =A0 std_logic; =A0 =A0 =A0 =A0 =A0 -- SDRAM DQML > =A0 =A0 s =A0 =A0 =A0: out =A0 std_logic_vector(6 downto 0); =A0-- 7-segm= ent LED > =A0 =A0 pps =A0 =A0: out =A0 std_logic_vector(6 downto 3) =A0-- outputs t= o > parallel port status bits > =A0 =A0 ); > end entity; > > architecture arch of test_board is > begin > > =A0 ce_n <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- = disable Flash RAM > > =A0 u0 : test_board_core > =A0 =A0 generic map( > =A0 =A0 =A0 FREQ =A0 =A0 =A0 =A0=3D> 100_000, > =A0 =A0 =A0 PIPE_EN =A0 =A0 =3D> true, > =A0 =A0 =A0 DATA_WIDTH =A0=3D> sData'length, > =A0 =A0 =A0 SADDR_WIDTH =3D> sAddr'length, > =A0 =A0 =A0 NROWS =A0 =A0 =A0 =3D> 8192, > =A0 =A0 =A0 NCOLS =A0 =A0 =A0 =3D> 512, > =A0 =A0 =A0 BEG_ADDR =A0 =A0=3D> 16#00_0000#, > =A0 =A0 =A0 END_ADDR =A0 =A0=3D> 16#FF_FFFF#, > =A0 =A0 =A0 BEG_TEST =A0 =A0=3D> 16#00_0000#, > =A0 =A0 =A0 END_TEST =A0 =A0=3D> 16#FF_FFFF# > =A0 =A0 =A0 ) > =A0 =A0 port map( > =A0 =A0 =A0 button_n =A0 =A0=3D> sw2, > =A0 =A0 =A0 clk =A0 =A0 =A0 =A0 =3D> clk, > =A0 =A0 =A0 sclkfb =A0 =A0 =A0=3D> sclkfb, > =A0 =A0 =A0 sclk =A0 =A0 =A0 =A0=3D> sclk, > =A0 =A0 =A0 cke =A0 =A0 =A0 =A0 =3D> cke, > =A0 =A0 =A0 cs_n =A0 =A0 =A0 =A0=3D> cs_n, > =A0 =A0 =A0 ras_n =A0 =A0 =A0 =3D> ras_n, > =A0 =A0 =A0 cas_n =A0 =A0 =A0 =3D> cas_n, > =A0 =A0 =A0 we_n =A0 =A0 =A0 =A0=3D> we_n, > =A0 =A0 =A0 ba =A0 =A0 =A0 =A0 =A0=3D> ba, > =A0 =A0 =A0 sAddr =A0 =A0 =A0 =3D> sAddr, > =A0 =A0 =A0 sData =A0 =A0 =A0 =3D> sData, > =A0 =A0 =A0 dqmh =A0 =A0 =A0 =A0=3D> dqmh, > =A0 =A0 =A0 dqml =A0 =A0 =A0 =A0=3D> dqml, > =A0 =A0 =A0 led =A0 =A0 =A0 =A0 =3D> s, > =A0 =A0 =A0 heartBeat =A0 =3D> pps(6) > =A0 =A0 =A0 ); > > end arch; > > thanks You need two things for sure: a schematic for the board, and a datasheet for the SDRAM device in particular that you're talking to. The ports you list suggest that this is the top level interface to an SDRAM, not to a controller. You either need to find source code for a controller for your chip, or write your own (which is a good educational experience but consider it an "advanced" topic not ideally suitable for a newbie). The datasheet will tell you what you have to do with the SDRAM pins you list in order to make the memory accesses happen. - Kenn