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Parallel processes

Is there any good reason to have two almost similar processes, with
almost similar sensitivity list?
I have a problem with a size of the design. I'm using  Lattice LC4128V
and currently the design is using 130/128 logic functions. In on vhdl
block there is two processes almost similar, like shown below. I got
the code from the other designer and I'm just starting with VHDL, so I
ask for your help. Can I save in logic elements by combining these two
processes and does it affect the functionality or timing in some way?

architecture ltr of dio_write is
  signal IO_WRITE_tmp	: std_logic;
begin
  process(AT_CLK, xRESET_IN)
  begin
    if(xRESET_IN = '0') then
 	D_WRITE <= '0';	   
    elsif (AT_CLK = '1' and AT_CLK'event) then 
       D_WRITE <= not AT_xWR;
    end if;	
  end process;
  
  process (D_WRITE, AT_CLK, xRESET_IN) 
   begin
     if(xRESET_IN = '0') then
     	IO_WRITE_tmp <= '0';
     elsif ( AT_CLK='1' and AT_CLK'event) then --D_WRITE='1' and
    	 IO_WRITE_tmp <= D_WRITE;
     end if;
   end process;
    IO_WRITE <= not ((not IO_WRITE_tmp) and (not AT_xWR));  
end rtl;"
0
tommi
12/28/2004 7:15:02 AM
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Tommy wrote:
> Can I save in logic elements by combining these two
> processes and does it affect the functionality or timing in some way?

In general you do not need to bother with that. The compiler is usually
smart enough to figure that out for itself, whether it's 2 processes or 1.

Regards,

Pieter Hulshoff

0
Pieter
12/28/2004 8:21:06 AM
"Pieter Hulshoff" <phulshof@xs4all.nl> wrote in message 
news:41d11772$0$4412$e4fe514c@dreader17.news.xs4all.nl...
> Tommy wrote:
>> Can I save in logic elements by combining these two
>> processes and does it affect the functionality or timing in some way?
>
> In general you do not need to bother with that. The compiler is usually
> smart enough to figure that out for itself, whether it's 2 processes or 1.
>
> Regards,
>
> Pieter Hulshoff
>
Think haedware.  What will the synthesis tool build.
I don't think combining processes will help.

Niv. 


0
Niv
12/28/2004 10:03:04 AM
Tommy wrote:
> I have a problem with a size of the design. I'm using  Lattice LC4128V
> and currently the design is using 130/128 logic functions. In on vhdl
> block there is two processes almost similar, like shown below. 
Actually the two sensitivity list should be identical since both 
processes simply represent a flip-flop.
> Can I save in logic elements by combining these two
> processes and does it affect the functionality or timing in some way?
Merging the processes won't help you reducing the amount of resources 
used, you'll still have two flip flops. The point is what your design is 
intended to do? Do you really need both flops?
0
Dippy
12/28/2004 1:04:03 PM
I think there are two problems with the code -
1. The DWRITE is multiply driven and maybe this is not what you want.
2. The process which has clock in sensitivity list shouldnt have any
other signal other than reset else you get mismatch in simulation and
systhesis. 

-Neo

0
zingafriend
12/29/2004 11:26:54 AM
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