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Serial in Parallel out

Hello folks,

In my entity i am getting serial-bit input and my expected output shld
hve odd bit at one port and even bit at other port. the clk for input
is twice as compared to output data rate(eg.Input clk:X Mhz,Output clk:
X/2 Mhz). I wrote the code but i am not getting the result as expected
Initally in the waveform (for first cycle with reference to input clk).
can anybody tell me where i went wrong ?

Thanks in advance,
ALI

CODE FOR SERIAL-BIT  TO 2-BIT PARALLEL
------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;


ENTITY STOP IS
PORT
(
CLK_A	: IN STD_LOGIC;
CLK_B	: IN STD_LOGIC;
RST	: IN STD_LOGIC;
EN_STOP	: IN STD_LOGIC;
S_IN	: IN STD_LOGIC;
I_CHAN	: OUT STD_LOGIC;
Q_CHAN	: OUT STD_LOGIC
);
END STOP;
-------------------------------------------------------------------
ARCHITECTURE ARCH_STOP OF STOP IS

SIGNAL I_CLK_B		: STD_LOGIC;
SIGNAL Q_CLK_B		: STD_LOGIC;
SIGNAL DFF_CLK_A  	: STD_LOGIC_VECTOR(1 DOWNTO 0);
-------------------------------------------------------------------
BEGIN

PROCESS_CLKA : PROCESS (CLK_A,RST)

BEGIN -- PROCESS_22MHZ
	IF RST = '0' THEN
		DFF_CLK_A <= "11";
	  ELSIF (CLK_A'EVENT AND CLK_A = '1') THEN
		IF (EN_STOP = '0' ) THEN
		DFF_CLK_A <= "11";
	  ELSE
		DFF_CLK_A(1) <= S_IN;
		DFF_CLK_A(0) <= DFF_CLK_A(1);
          END IF;
	END IF;
END PROCESS PROCESS_CLKA;
-----------------------------------------------------------

PROCESS_CLKB : PROCESS(CLK_B,RST)
BEGIN -- PROCESS_11MHZ
         IF RST = '0' THEN
		I_CLK_B <= '1';
		Q_CLK_B <= '1';
	ELSIF (CLK_B'EVENT AND CLK_B = '1') THEN
          IF (EN_STOP = '0') THEN
                I_CLK_B <= '1';
		Q_CLK_B <= '1';
	ELSE
		I_CLK_B <= DFF_CLK_A(0);
		Q_CLK_B <= DFF_CLK_A(1);
	END IF;
	END IF;
END PROCESS PROCESS_CLKB;
-------------------------------------------------------------------
	I_CHAN <= I_CLK_B;
	Q_CHAN <= Q_CLK_B;


END ARCH_STOP;
-------------------------------------------------------------------


TEST BENCH FOR THE ABOVE ENTITY:


-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------
ENTITY TB_STOP IS
END TB_STOP;
-------------------------------------------------------------------
ARCHITECTURE ARCH_TB_STOP OF TB_STOP IS
-------------------------------------------------------------------

COMPONENT STOP
PORT
(
CLK_A	: IN STD_LOGIC;
CLK_B	: IN STD_LOGIC;
RST	: IN STD_LOGIC;
EN_STOP	: IN STD_LOGIC;
S_IN	: IN STD_LOGIC;
I_CHAN	: OUT STD_LOGIC;
Q_CHAN	: OUT STD_LOGIC
);
END COMPONENT;
-------------------------------------------------------------------

SIGNAL CLK_A	: STD_LOGIC := '0';
SIGNAL CLK_B	: STD_LOGIC := '0';
SIGNAL RST 	: STD_LOGIC := '1';
SIGNAL EN_STOP 	: STD_LOGIC := '0';
SIGNAL S_IN 	: STD_LOGIC;
SIGNAL I_CHAN 	: STD_LOGIC;
SIGNAL Q_CHAN 	: STD_LOGIC;
CONSTANT INPUT 	: STD_LOGIC_VECTOR(31 DOWNTO 0)
	:= "00110011001100110011001100110011";
-------------------------------------------------------------------
BEGIN

UUT : STOP
PORT MAP
(
CLK_A 	=> CLK_A,
CLK_B 	=> CLK_B,
RST 	=> RST,
EN_STOP	=> EN_STOP,
S_IN 	=> S_IN,
I_CHAN 	=> I_CHAN,
Q_CHAN 	=> Q_CHAN
);

--STIMULUS

CLK_A 	<=  NOT CLK_A AFTER 4 NS;
CLK_B 	<=  NOT CLK_B AFTER 8 NS;
RST 	<= '0','1' AFTER 2 NS;
EN_STOP <= '0','1' AFTER 3 NS;

DRIVE_BIT:PROCESS
BEGIN
FOR I IN INPUT'RANGE LOOP
	S_IN <= INPUT(I);
WAIT UNTIL RISING_EDGE(CLK_A);
END LOOP;
END PROCESS DRIVE_BIT;


END ARCH_TB_STOP;
-------------------------------------------------------------------

0
jahaya (17)
10/12/2005 9:15:09 AM
comp.lang.vhdl 6430 articles. 2 followers. Post Follow

2 Replies
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jahaya@gmail.com wrote:
> Hello folks,
>
> In my entity i am getting serial-bit input and my expected output shld
> hve odd bit at one port and even bit at other port. the clk for input
> is twice as compared to output data rate(eg.Input clk:X Mhz,Output clk:
> X/2 Mhz). I wrote the code but i am not getting the result as expected
> Initally in the waveform (for first cycle with reference to input clk).
> can anybody tell me where i went wrong ?
>
> Thanks in advance,
> ALI
>
> CODE FOR SERIAL-BIT  TO 2-BIT PARALLEL
> ------------------------------------------------------------------
> LIBRARY IEEE;
> USE IEEE.STD_LOGIC_1164.ALL;
> USE IEEE.NUMERIC_STD.ALL;
>
>
> ENTITY STOP IS
> PORT
> (
> CLK_A	: IN STD_LOGIC;
> CLK_B	: IN STD_LOGIC;
> RST	: IN STD_LOGIC;
> EN_STOP	: IN STD_LOGIC;
> S_IN	: IN STD_LOGIC;
> I_CHAN	: OUT STD_LOGIC;
> Q_CHAN	: OUT STD_LOGIC
> );
> END STOP;
> -------------------------------------------------------------------
> ARCHITECTURE ARCH_STOP OF STOP IS
>
> SIGNAL I_CLK_B		: STD_LOGIC;
> SIGNAL Q_CLK_B		: STD_LOGIC;
> SIGNAL DFF_CLK_A  	: STD_LOGIC_VECTOR(1 DOWNTO 0);
> -------------------------------------------------------------------
> BEGIN
>
> PROCESS_CLKA : PROCESS (CLK_A,RST)
>
> BEGIN -- PROCESS_22MHZ
> 	IF RST = '0' THEN
> 		DFF_CLK_A <= "11";
> 	  ELSIF (CLK_A'EVENT AND CLK_A = '1') THEN
> 		IF (EN_STOP = '0' ) THEN
> 		DFF_CLK_A <= "11";
> 	  ELSE
> 		DFF_CLK_A(1) <= S_IN;
> 		DFF_CLK_A(0) <= DFF_CLK_A(1);
>           END IF;
> 	END IF;
> END PROCESS PROCESS_CLKA;
> -----------------------------------------------------------
>
> PROCESS_CLKB : PROCESS(CLK_B,RST)
> BEGIN -- PROCESS_11MHZ
>          IF RST = '0' THEN
> 		I_CLK_B <= '1';
> 		Q_CLK_B <= '1';
> 	ELSIF (CLK_B'EVENT AND CLK_B = '1') THEN
>           IF (EN_STOP = '0') THEN
>                 I_CLK_B <= '1';
> 		Q_CLK_B <= '1';
> 	ELSE
> 		I_CLK_B <= DFF_CLK_A(0);
> 		Q_CLK_B <= DFF_CLK_A(1);
> 	END IF;
> 	END IF;
> END PROCESS PROCESS_CLKB;
> -------------------------------------------------------------------
> 	I_CHAN <= I_CLK_B;
> 	Q_CHAN <= Q_CLK_B;
>
>
> END ARCH_STOP;
> -------------------------------------------------------------------
>
>
> TEST BENCH FOR THE ABOVE ENTITY:
>
>
> -------------------------------------------------------------------
> LIBRARY IEEE;
> USE IEEE.STD_LOGIC_1164.ALL;
> USE IEEE.NUMERIC_STD.ALL;
> -------------------------------------------------------------------
> ENTITY TB_STOP IS
> END TB_STOP;
> -------------------------------------------------------------------
> ARCHITECTURE ARCH_TB_STOP OF TB_STOP IS
> -------------------------------------------------------------------
>
> COMPONENT STOP
> PORT
> (
> CLK_A	: IN STD_LOGIC;
> CLK_B	: IN STD_LOGIC;
> RST	: IN STD_LOGIC;
> EN_STOP	: IN STD_LOGIC;
> S_IN	: IN STD_LOGIC;
> I_CHAN	: OUT STD_LOGIC;
> Q_CHAN	: OUT STD_LOGIC
> );
> END COMPONENT;
> -------------------------------------------------------------------
>
> SIGNAL CLK_A	: STD_LOGIC := '0';
> SIGNAL CLK_B	: STD_LOGIC := '0';
> SIGNAL RST 	: STD_LOGIC := '1';
> SIGNAL EN_STOP 	: STD_LOGIC := '0';
> SIGNAL S_IN 	: STD_LOGIC;
> SIGNAL I_CHAN 	: STD_LOGIC;
> SIGNAL Q_CHAN 	: STD_LOGIC;
> CONSTANT INPUT 	: STD_LOGIC_VECTOR(31 DOWNTO 0)
> 	:= "00110011001100110011001100110011";
> -------------------------------------------------------------------
> BEGIN
>
> UUT : STOP
> PORT MAP
> (
> CLK_A 	=> CLK_A,
> CLK_B 	=> CLK_B,
> RST 	=> RST,
> EN_STOP	=> EN_STOP,
> S_IN 	=> S_IN,
> I_CHAN 	=> I_CHAN,
> Q_CHAN 	=> Q_CHAN
> );
>
> --STIMULUS
>
> CLK_A 	<=  NOT CLK_A AFTER 4 NS;
> CLK_B 	<=  NOT CLK_B AFTER 8 NS;
> RST 	<= '0','1' AFTER 2 NS;
> EN_STOP <= '0','1' AFTER 3 NS;
>
> DRIVE_BIT:PROCESS
> BEGIN
> FOR I IN INPUT'RANGE LOOP
> 	S_IN <= INPUT(I);
> WAIT UNTIL RISING_EDGE(CLK_A);
> END LOOP;
> END PROCESS DRIVE_BIT;
>
>
> END ARCH_TB_STOP;
> -------------------------------------------------------------------


----------------------------------------------------------------------------------------------------------------------------------------------------
hii...
m sending u a simple serial-in parallel out code in vhdl. write ur tb n
test it.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity shift is
  port(clk, reset, load : in  std_logic;
       data_in : in std_logic;
       data_out : out std_logic_vector(15 downto 0));
end shift;

architecture rtl of shift is
signal s: std_logic_vector(15 downto 0);
begin
 process(clk)
 begin
    if (reset = '1') then
         s <= (others => '0');
    elsif (clk = '1' and clk'event) then
         if (load = '1') then
             s <= data_in & s(15 downto 1);
         else
		      s <= (others => '0');  --right shift
         end if;
    end if; 
end process; 
data_out <= s; 
end rtl; 

bye

0
Abbs
10/20/2005 7:44:11 AM
Abbs wrote:

> m sending u a simple serial-in parallel out code in vhdl. write ur tb n
> test it.

Here's rev2.

         -- Mike Treseler

http://home.comcast.net/~mike_treseler/shift_rev2.vhd
http://home.comcast.net/~mike_treseler/shift_rev2.pdf
0
Mike
10/20/2005 5:36:02 PM
Reply: