Hi everybody, I'd like to know if there is any smart way to extend the sign of std_logic_vector for exemple : data_in : in std_logic_vector(11 downto 0); data_out : out std_logic_vector(13 downto 0); I want to adjust data_in to data_out size, so what i used to do is: data_out <= data_in(11) & data_in(11) & data_in; But for huge different size it's painfull and not really nice. Is there a smarter way to do it?? May be I should do a function with a loop that do it?? Thank you

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11/21/2006 9:37:12 AM

kclo4 a �crit : > Hi everybody, > > I'd like to know if there is any smart way to extend the sign of > std_logic_vector > > for exemple : > > data_in : in std_logic_vector(11 downto 0); > data_out : out std_logic_vector(13 downto 0); > > I want to adjust data_in to data_out size, so what i used to do is: > > data_out <= data_in(11) & data_in(11) & data_in; > > But for huge different size it's painfull and not really nice. > Is there a smarter way to do it?? May be I should do a function with a > loop that do it?? Use ieee.numeric_std package, signed vectors instead of std_logic_vector and resize function. data_out <= resize(data_in, data_out'length); Nicolas

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11/21/2006 9:54:05 AM

kclo4 a �crit : > Hi everybody, > > I'd like to know if there is any smart way to extend the sign of > std_logic_vector > > for exemple : > > data_in : in std_logic_vector(11 downto 0); > data_out : out std_logic_vector(13 downto 0); > > I want to adjust data_in to data_out size, so what i used to do is: > > data_out <= data_in(11) & data_in(11) & data_in; > > But for huge different size it's painfull and not really nice. > Is there a smarter way to do it?? May be I should do a function with a > loop that do it?? > > Thank you You have it for free in the std_logic_arith package: function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; [...] data_out <= SXT(data_in, data_out'LENGTH); You also have the EXT function, which is the simple extension function _without_ sign extension.

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11/21/2006 1:29:33 PM

Many users don't recommend using non-ieee packages such as std_logic_arith, etc. that were developed by synopsys and compiled into the ieee library without ieee permission/standardization. Since they are not standard, their implementation can and does vary between vendors of simulation and synthesis tools. Better to type a little more and use ieee standard packages that are uniform in their implementation across all vendors. If you need to keep data_in and data_out as SLV: data_out <=3D std_logic_vector(resize(signed(data_in), data_out'length)); Andy OL wrote: > kclo4 a =E9crit : > > Hi everybody, > > > > I'd like to know if there is any smart way to extend the sign of > > std_logic_vector > > > > for exemple : > > > > data_in : in std_logic_vector(11 downto 0); > > data_out : out std_logic_vector(13 downto 0); > > > > I want to adjust data_in to data_out size, so what i used to do is: > > > > data_out <=3D data_in(11) & data_in(11) & data_in; > > > > But for huge different size it's painfull and not really nice. > > Is there a smarter way to do it?? May be I should do a function with a > > loop that do it?? > > > > Thank you > > You have it for free in the std_logic_arith package: > function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTO= R; > > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_SIGNED.ALL; > [...] > data_out <=3D SXT(data_in, data_out'LENGTH); > > You also have the EXT function, which is the simple extension function > _without_ sign extension.

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11/21/2006 1:55:00 PM

Or if you use appropriately constrained subtypes of integer for data_out and data_in: data_out <=3D data_in; Andy Nicolas Matringe wrote: > kclo4 a =E9crit : > > Hi everybody, > > > > I'd like to know if there is any smart way to extend the sign of > > std_logic_vector > > > > for exemple : > > > > data_in : in std_logic_vector(11 downto 0); > > data_out : out std_logic_vector(13 downto 0); > > > > I want to adjust data_in to data_out size, so what i used to do is: > > > > data_out <=3D data_in(11) & data_in(11) & data_in; > > > > But for huge different size it's painfull and not really nice. > > Is there a smarter way to do it?? May be I should do a function with a > > loop that do it?? > > Use ieee.numeric_std package, signed vectors instead of std_logic_vector > and resize function. >=20 > data_out <=3D resize(data_in, data_out'length); >=20 > Nicolas

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11/21/2006 1:57:30 PM

Nicolas Matringe schrieb: > Use ieee.numeric_std package, signed vectors instead of std_logic_vector > and resize function. > > data_out <= resize(data_in, data_out'length); Respectively with std_ulogic_vector and the desired conversions: -- either data_out<=std_ulogic_vector(resize(unsigned(data_in), data_out'length)); -- or data_out<=std_ulogic_vector(resize( signed(data_in), data_out'length)); (I only want to point it out that sign extension of std_ulogic_vectors strongly depends on the fact whether signed or unsigned data representation is desired.) Ralf

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11/21/2006 4:13:44 PM

There is no "sign extension" of unsigned representations, since there is no sign bit. A resize of an unsigned representation to a larger size just appends enough zeroes to fit, whereas sign extension replicates the MSB enough times to fit. The numeric_std.resize() function is overloaded to perform a sign extend operation when called with a signed argument and return value (assuming it is increasing the size of the argument). Andy Ralf Hildebrandt wrote: > Nicolas Matringe schrieb: > > > > Use ieee.numeric_std package, signed vectors instead of std_logic_vector > > and resize function. > > > > data_out <= resize(data_in, data_out'length); > > Respectively with std_ulogic_vector and the desired conversions: > > -- either > data_out<=std_ulogic_vector(resize(unsigned(data_in), data_out'length)); > -- or > data_out<=std_ulogic_vector(resize( signed(data_in), data_out'length)); > > (I only want to point it out that sign extension of std_ulogic_vectors > strongly depends on the fact whether signed or unsigned data > representation is desired.) > > Ralf

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11/21/2006 10:30:20 PM

Andy schrieb: > There is no "sign extension" of unsigned representations, since there > is no sign bit. A resize of an unsigned representation to a larger size > just appends enough zeroes to fit, whereas sign extension replicates > the MSB enough times to fit. Yes, I know - but I wanted to point out, that nobody can say, what is inside a std_logic_vector: just bits, signed or unsigned data. And even adding zeros while resizing an unsigned vector is some kind of sign extension, because an unsigned vector has always an implicit zero as sign. Ralf

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11/22/2006 8:41:48 AM

kclo4 wrote: > Hi everybody, > > I'd like to know if there is any smart way to extend the sign of > std_logic_vector > > for exemple : > > data_in : in std_logic_vector(11 downto 0); > data_out : out std_logic_vector(13 downto 0); > > I want to adjust data_in to data_out size, so what i used to do is: > > data_out <= data_in(11) & data_in(11) & data_in; > > But for huge different size it's painfull and not really nice. > Is there a smarter way to do it?? May be I should do a function with a > loop that do it?? > > Thank you Don't need any libraries or loops if you do this: data_out(11 downto 0) <= data_in; data_out(13 downto 12) <= (13 downto 12 => data_in(11));

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11/22/2006 6:51:47 PM

Ralf Hildebrandt a �crit : > (I only want to point it out that sign extension of std_ulogic_vectors > strongly depends on the fact whether signed or unsigned data > representation is desired.) I assumed that sign extension was only needed for signed vectors. Nicolas

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11/22/2006 9:21:35 PM

Thanks you all for your usefull answers, > Don't need any libraries or loops if you do this: > > data_out(11 downto 0) <= data_in; > data_out(13 downto 12) <= (13 downto 12 => data_in(11)); I like this way but shouldn't it be? : data_out(13 downto 12) <= (others => data_in(11)); Probably both work?, I will try myself to check Thanks alexis

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11/23/2006 9:38:06 AM

Can someone tell me when to use MOVSX and when to use MOVZX ? for example, the following disassembled code use MOVSX, why ? mov [ebp+var_4], 0 loc_0_4010DB: mov eax, [ebp+arg_0] movsx ecx, byte ptr [eax] test ecx, ecx jz short loc_0_401159 mov edx, [ebp+arg_0] movsx eax, byte ptr [edx] cmp eax, 41h jl short loc_0_401113 sugaray <ruicui@sohu.com> wrote: >...

I would like to digitally sign the open source Python extensions I produce. I produce source code (zip file) as well as pre-built binaries for Windows (all Python versions from 2.3 to 3.1). I can sign the source using my PGP key no problem. I could also sign the Windows binaries that way but Windows users are unlikely to have PGP and the Google code downloads page would look even worse having another 8 or 9 .asc files. The Windows Python distribution is signed by PGP and the normal Microsoft way using a Verisign class 3 cert. (If you read their issuer statement it ultimately says the cert...

Hi, Could someone please explain what sign-extension means? If I have a hex number 0x55, how does this get sign-extended? Can a sign-extended counterpart be equal to -91? In a program I'm expecting 0x55 in return from a function whereas I am getting -91 every time.. does this mean anything? Thanks Sona "Sona" <sona.gardner@nospam.com> wrote in message news:3f71ba78$1@clarion.carno.net.au... > Hi, > > Could someone please explain what sign-extension means? If I have a hex > number 0x55, how does this get sign-extended? Try asking this question in comp.p...

Hi, I am a newcomer to VHDL and the Xilinx ISE. I have no previous experience and my knowledge of the ISE and VHDL are rather low :(. I needed to use the 16pt. IFFT core and so I used the CORE Generator to generate it. Now the problem is that the core expects 2's complemented inputs and outputs in the form of STD_LOGIC_VECTOR. I had a look at the VHDL datatypes and saw that the SIGNED type is suitable for 2s complement representations .. now I am really confused about all these and have no clue what to do .. I tried changing the std_logic_vector(a:b) lines to SIGNED(a:b) but the compile...

Is there any way I can read in a file of negative and positive integers into my VHDL testbench and convert them to hex values? Or does anybody have a program to convert them? Salman "salman sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message news:cpvh5j$qo$1@skates.gsfc.nasa.gov... > Is there any way I can read in a file of negative and positive integers > into my VHDL testbench and convert them to hex values? Or does anybody > have a program to convert them? > > Salman You can read in integers using textio, and just reading into an integer. e.g. use ...

I would like to design a 16 to 32-bit sign extension unit. I would like to preserve the number's sign (positive/negative). So I guess after I append digits to the MSB then I would need to take care of the sign's, how could I do this in verilog? On Jan 27, 4:23=A0pm, rekz <aditya15...@gmail.com> wrote: > I would like to design a 16 to 32-bit sign extension unit. I would > like to preserve the number's sign (positive/negative). So I guess > after I append digits to the MSB then I would need to take care of the > sign's, how could I do this in verilog? is it just as simple as this: module SignExtension(a, result); input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result =3D { 16{a[31]}, a }; endmodule This is a multi-part message in MIME format. ----------------275652565738620419 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit On 2010-01-27 15:30:27 -0800, rekz said: > On Jan 27, 4:23�pm, rekz <aditya15...@gmail.com> wrote: >> I would like to design a 16 to 32-bit sign extension unit. I would >> like to preserve the number's sign (positive/negative). So I guess >> after I append digits to the MSB then I would need to take care of the >> sign's, how could I do this in verilog? > > is it just as simple as this: > > module SignExtension(a, result); > > input [15:0] a; /...

I'm working on a program that will be parsing a protocol. My basic storage element type is an array of characters or char*. The reason I am using char* is because many of the socket and stream functions I'll be using take char* as a parameter. What I am seeing with my program is that when bit 7 is true, my integers are being sign extended. Below is a program that should demonstrate my problem. I am encountering this problem in a checksum loop that is adding unsigned bytes together. As soon as bit7 is set my numbers become huge because something is sign extending the high-byte. I...

Hello! I have a problem related to a macro. I know that macros are deprecated in C++ and that an inline function should be used instead, but the answer to my question would probably make my understanding of the language more profound. And it would convince me that macros are really as bad as everybody says... ;-) Well, here's the problem. I want to write a macro that composes a 32 bit from two 16 bit values, in order to facilitate the creation of certain type identifiers as follows: #define MAKE_IDENTIFIER( hi, lo )\ ( (unsigned long) (unsigned short) ( hi ) << 16 ) |...

I was told that this will work in Verilog. acc = { 3{ir[12]}, imm }; However, Modelsim reports an error: syntax error, unexpected ',', expecting '}' I know that $signed(imm) works. I just want to know what is wrong with that method. On 03/03/13 18:54, valtih1978 wrote: > I was told that this will work in Verilog. > > acc = { 3{ir[12]}, imm }; > > However, Modelsim reports an error: syntax error, unexpected ',', > expecting '}' > Replication requires 2 pairs of braces, i.e. acc = { {3{ir[12]}}, imm}; regard...

Hi, I've been having trouble trying to find the html code command for how to make the sign that when you click something wrong it flashes up and makes a tone with the speakers on and has a customized message. If you know the code please follow up. Any possible information partaining to my requests is very highly appreciated!!! Thank you in advance!!! I know you smart people can find an answer!!! (I'd be glad to hear from you!!!) Neil Varshneya wrote: > I've been having trouble trying to find the html code command for how > to make the sign that when you click...

I recall a few months ago coming across an article allowing for encoding (or converting?) xml and html documents into sign language as well as brail for deaf and blind people, and that they were pending an ISO designations. I cannot seem to find any information on this. From what I recall they were supposed to be use able in <meta> charset or so tags. Thanks in advance for any help on this. Steve K. wrote: > I recall a few months ago coming across an article allowing for encoding > (or converting?) xml and html documents into sign language This seems slightly dubious -...

woe be unto he who abuses the right holy GBIT* macros with signed integers; for verily will he be smitten by lust for sign extension. i say unto you, he will be screwed. (i'm looking at you devpnp.) - erik p.s. maybe a few ugly casts in the macros? it is quite a silly bug. or heven forbid, make 'em functions? ...

Well i had a though time extracting information from previous threads on the above three topics ....its soo much information and it creates more confusion ... kindly guide me to some well written articles on these topics... 1. Integral promotion : What i understand: " If two types are intermixed then the type with smaller capacity is promoted to the type with the larger capacity" ..i am sure i am wrong here . 2. Sign extension: what i understand: whenever say a char is promoted to int the msb of char is copied in the extra bits in the msb of the int ...i.e char= 100...

is their standard way to represent signed numbers in binary? I know there is two's complement notation etc etc. but is there a general standard to do this in binary notation or do people tend to use two's complement? - Kingsley ...

In the simple pipelines in Hennessy & Patterson's CA:aQA immediates are handled by applying a sign extension in the decode stage. ISTM that with a certain encoding of the immediate field, it would become reasonable to instead modify the opcode (if the immediate's sign bit is set) to invert the immediate or invert and assert carry-in (i.e., make ADDI a SUBI). This would avoid speculative work, but more importantly instruction buffers could be smaller. (This seems an obvious benefit, but the early RISCs did not choose such encodings. Was the additional compiler complexity...

Hello. Does anyone have a synthesizable implementation of 2's complement integers for FPGA? The integers in question are of std_logic_vector of different number of bits. It does not necessarily need any carry as the precision I need isn't very crucial, but the sign is of course important. Would be good if anyone has any useful source, or if someone can point me in the direction of an algorithm for this. Cheers, Dan I suggest you post this question on comp.arch.fpga or comp.dsp group. You might get some replies.. ...

for example, In the code constant A : std_logic_vector(7 downto 0) := conv_std_logic_vector(16#12#, 8); what does the 16#12# mean here? On Thu, 10 Jul 2008 03:00:19 -0700 (PDT), bigyellow wrote: > constant A : std_logic_vector(7 downto 0) := >conv_std_logic_vector(16#12#, 8); > >what does the 16#12# mean here? Hex radix, like "0x12" in C, or "'h12" in Verilog. Also 2#010010# -- binary 8#22# -- octal -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services D...

I've looked up google, but I can't seem to find a concise summary about the differences between VHDL 87/93/2002. What are they? And what's the next version of VHDL? Someone wrote: "I've looked up google, but I can't seem to find a concise summary about the differences between VHDL 87/93/2002. What are they?" VHDL93 has many differences from VHDL87, these are mostly additions amongst which are shared variables and directly instantiating a component by using the entity name; and at least one change to filehandling which is not backwards compatible. You may ...

Hi, I have some 24bit audio data (stored in an unsigned int). I have to sign extend it to 32 bit. From what I understand, I just look at bit 23 (counting from bit0) which is the sign-bit. If it is 1 then I place 1's in bit23 to bit31. If it is zero then I don't need to do anything. Now...is there a fast way of doing that on SHARC ADSP 21469 ? A built- in function or something? I haven't been able to find anything in the manuals (maybe I am overlooking something). Thanks "Mauritz Jameson" <mjames2393@gmail.com> wrote in message news:2ea9ca25-...

I'm a lazy coder and want to use the intrinsic method ".sum()" to tabulate the total of a 2D array. logic signed [15:0] array [0:255]; // lots of widgets! // the old fashioned way logic signed [31:0] sum; for ( int i = 0; i < $size(array); ++i ) sum = sum + array[i]; // the new and superior way logic signed [31:0] sum; sum = array.sum(); // INCORRECT RESULT! ---------------- Ok, after reading Chris Spear's "Systemverilog for Verification", there was a warning against this gotcha. Basically, ".sum()" performs the computation w...

I understand Verilog 2001 added the ">>>" operator for sign extension right shift. But how does it work? I was implementing a shifter unit as part of an ALU. I had done the following: assign #1 rarithmetic = b >>> shiftamount; where b and shiftamount were both input [31:0] vectors. However, the sign extension does not occur. I had b = 0xd1200000 and the result was 0x0000d120 instead of 0xffffd120. I know there is also the "signed" keyword but it didn't seem to have any effect when I tried "input signed [31:0] ...". What am I doing...

I'm trying to elegantly convert a std_logic_vector(upper downto lower) to an integer without sign extension using ieee.numeric_std with upper and lower taking on values from 31 to 0 and with upper >= lower. I cannot seem to find a syntax that doesn't generate truncation warnings, or relies on doing some comparison. If I use: i:= to_integer( signed( slv(upper downto lower))); I'll get sign extension if upper==lower (which I don't want). To avoid sign extension, I've tried: i:= to_integer( signed( '0' & slv(upper downto lower))); Tha...

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