variable L: Line;
variable Tim: time;
variable Int: integer;
variable cha: character;
variable str : string(1 to 6);
READLINE(F,L);
READ(L, Tim);
READ(L, Int);
READ(L, cha);
READ(L, Str);
READ(L, Int);
for the above code, what will i get if the input file, F has..
100 NS 99 ABCDEF 27
as the input stimuli?
|
|
0
|
|
|
|
Reply
|
Zhane
|
4/25/2009 9:52:22 AM |
|
On Sat, 25 Apr 2009 02:52:22 -0700 (PDT), Zhane wrote:
>variable L: Line;
>variable Tim: time;
>variable Int: integer;
>variable cha: character;
>variable str : string(1 to 6);
>
>READLINE(F,L);
>READ(L, Tim);
>READ(L, Int);
>READ(L, cha);
>READ(L, Str);
>READ(L, Int);
>
>for the above code, what will i get if the input file, F has..
>100 NS 99 ABCDEF 27
>
>as the input stimuli?
I've seen that example somewhere before....
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
|
|
0
|
|
|
|
Reply
|
Jonathan
|
4/25/2009 2:54:14 PM
|
|
|
1 Replies
252 Views
(page loaded in 0.008 seconds)
Similiar Articles: std.textio.all procedure read - comp.lang.vhdlvariable L: Line; variable Tim: time; variable Int: integer; variable cha: character; variable str : string(1 to 6); READLINE(F,L); READ(L, Tim); REA... boolean to std_logic - comp.lang.vhdlHow to write testbench file? - comp.lang.vhdl "library ieee; use ieee.std_logic_1164.all; entity FSM_CorePWM is GENERIC (PWM ... uses it will take advantage of it because ... Including Verilog parameter in VHDL - comp.lang.vhdlstd.textio.all procedure read - comp.lang.vhdl Including Verilog parameter in VHDL - comp.lang.vhdl std.textio.all procedure read - comp.lang.vhdl... Reading from and writing to a text file in verilog hdl - comp.arch ...std.textio.all procedure read - comp.lang.vhdl... Design Know-how VHDL * Verilog ... How to write testbench file? - comp.lang.vhdl ... using the READLINE and READ ... Some text processing questions - comp.lang.vhdlstd.textio.all procedure read - comp.lang.vhdl Some text processing questions - comp.lang.vhdl My rule of thumb is to use textio for reading ... remove_comment > >This is ... Fortran 95 equivalent of read(..., POS=...) - comp.lang.fortran ...std.textio.all procedure read - comp.lang.vhdl Fortran 95 equivalent of read(..., POS=...) - comp.lang.fortran ..... only '03 feature the code has is this ONE line: read ... Braces within a string - comp.lang.awkstd.textio.all procedure read - comp.lang.vhdl Braces within a string - comp.lang.awk... Nothing would be done at all, Stay Fit ... need to pass following string as an ... comp.lang.vhdl - page 33If this is done with the TextIO package, then ... count-up at the same time when I read the ... 10/1/2003 9:05:48 AM) Hi all, Is there any operator to divide a std_logic_vector ... Image block - comp.soft-sys.matlabAnyone could help me to find the procedure for it. ... pixel in the block by the median, mean, or standard % deviation of all ... cd(fileparts(which(mfilename))); end % Read ... converting a character string into a variable name - comp.lang ...... along with the data and a select * would give you all ... by using Matlab syntax to generate a Fortran READ() :) )... ... types, you could make WrVar an overloaded module procedure. std.textio.all procedure read - comp.lang.vhdl | Computer Groupvariable L: Line; variable Tim: time; variable Int: integer; variable cha: character; variable str : string(1 to 6); READLINE(F,L); READ(L, Tim); REA... std.textio.all procedure read - FPGA Groupsvariable L: Line; variable Tim: time; variable Int: integer; variable cha: character; variable str : string(1 to 6); READLINE(F,L); READ(L, Tim); READ 7/25/2012 2:59:35 AM
|