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Verilog Implementation of FIR Filter
HI,
I want the verilog implementation of N-Tap FIR filter.... I am bit in
a fix, to use a Distributed arithmetic or MAC unit... I suppose if I
am using Vertex 4 FPGA's that have inbuilt Multiplier, then I dont
need DA or MAC unit??
Kindly suggest...
Regards
Rahul
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Rahul
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2/19/2008 12:34:50 PM |
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On Feb 19, 5:34=A0pm, Rahul Iyer <rahul.hariha...@gmail.com> wrote:
> HI,
> I want the verilog implementation of N-Tap FIR filter.... I am bit in
> a fix, to use a Distributed arithmetic or MAC unit... I suppose if I
> am using Vertex 4 FPGA's that have inbuilt Multiplier, then I dont
> need DA or MAC unit??
> Kindly suggest...
>
> Regards
> Rahul
I think u can design by usin Matlab. There u can find a system
generate option in edatool design. You can design whichever filter u
want, and in which language u want, u can
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gally
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2/20/2008 6:48:46 AM
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