Hi, I have small problems understanding what the 1076-1993 Ch. 4.3.2.2/490 "The type of the actual (after applying the conversion function or type conversion. if present in the actual part) must be the same as the type of the corresponding formal, if the mode of the formal is IN, INOUT, or LINKAGE, and if the actual is not open. Similarly, if the mode of the formal is OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not open, then the type of the formal (after applying the conversion function or type conversion, if present in the formal part) must be the same as the corresponding ac...

I was considering what it will take to implement a bi-directional switch in VHDL and found this by Peter Ashenden. The method is pretty much what I had thought of, but it does have one problem where a high impedance on either side of the switch will not be conveyed to the other once the bus has been set to a 1 or 0 state. In essence, this is not really a switch, but rather a bus keeper. function weaken ( value : in std_logic ) return std_logic is type lookup_array is array (std_logic) of std_logic; constant lookup_weaker_value : lookup_array := ('U'=>'U', ...

I've looked up google, but I can't seem to find a concise summary about the differences between VHDL 87/93/2002. What are they? And what's the next version of VHDL? Someone wrote: "I've looked up google, but I can't seem to find a concise summary about the differences between VHDL 87/93/2002. What are they?" VHDL93 has many differences from VHDL87, these are mostly additions amongst which are shared variables and directly instantiating a component by using the entity name; and at least one change to filehandling which is not backwards compatible. You may ...

Hey i am pretty green at this VHDL... can someone tell me the error in this code.. : library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_unsigned.all; entity Test is port( b: in std_logic; a: out std_logic_vector(7 downto 0)); end Test; architecture eksempel of Test is signal a_old,a_new : std_logic_vector(7 downto 0); begin test_if:process(b) begin if b='1' then a_new <= a_old + 1; end if; a<=a_new; end process test_if; end eksempel; it was suposed to add 1 to A regards Kasper > can someone tell me the error in this code.. : ...

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hello, please i am looking for someone who can help me to solve my pb. this is my code : Bonjour a tous, je cherche de l'aide pour mon projet sur VHDL: mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. voici mes codes: --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity Lane is port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; DATA_IN : IN std_logic; FPP_SEC_EN : IN std_logic; FPP_TURN_S...

Would it be feasible to implement a VHDL interpreter in Forth (i.e. is VHDL sufficiently clearly defined)? -marcel Marcel Hendrix schrieb: > Would it be feasible to implement a VHDL interpreter in Forth > (i.e. is VHDL sufficiently clearly defined)? > > -marcel > Hmm, your short question is a bit too cryptic for me. At least Google shows a few hits when searching for VERILOG and FORTH. The same is true for VHDL and SIMULATOR. Then we have f.ex. http://www.verilog.net/free.html What were you aiming at? Andreas On 12 May, 20:44, m...@iae.nl (Marcel Hendrix) wrote: &g...

i want to know is there any constructs similar to jump with condition to go to start is available in vhdl ...

can anyone help me and tell me what this program exactly do please? 1 ENTITY EX8 IS 2 GENERIC (n : NATURAL :=4); 3 PORT (clk, rst : IN BIT; 4 in1, in2 : IN BIT_VECTOR (n-1 DOWNTO 0); 5 opt : OUT BIT_VECTOR (n-1 DOWNTO 0)); 6 END EX8; 7 ARCHITECTURE behave OF EX8 IS 8 SIGNAL sopt : BIT_VECTOR (n-1 DOWNTO 0); 9 SIGNAL chng : BIT; 10 BEGIN 11 P0: PROCESS (clk, rst) 12 BEGIN 13 IF rst='1' THEN chng<='0'; 14 ELSIF clk'EVENT AND clk='1' THEN 15 IF sopt=in2 THEN chng<='1'; 16 ELSIF sopt=in1 THEN chng<='0'; 17 END IF...

Now, I used the state machine to apply to VHDL. In my case, there are two states, S0 and S1. When I press a button, S0 is transit to S1 such that the LED display some of the segments,like segment a,b,c. And press this button again, S1 is back to S0. How can I present in VHDL so that the LED display in segment a,b,c ? Thanks!! Why don't you have a look at a common VHDL book ? There are so many simple examples which show how to describe a state machine ... You could design your state machine on a piece of paper first,=20 later try to describe in VHDL ... Rgds Andr=E9 if you are trying ...

How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? The signals a and b are 32 bit signed fix point numbers (std_logic_vector (31 downto 0)). Marko S schrieb: > How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? > The signals a and b are 32 bit signed fix point numbers (std_logic_vector > (31 downto 0)). how accurate? how fast? latency? a table with 64 Bits input, 32 Bits output will not fit into an FPGA (but if you need the result with low latency, you might store some precomputed data in an external ram) or you could do something like max(a, b) + 0.5*min(a,b...

Hello, I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro FPGA. I will be getting IQ data on which I'll do the demodulation. However, the IQ data has varying phase and frequency offsets which need to be corrected before hard decision decoding can be carried out. Has anyone implemented frequency and phase offset removal using VHDL/fixed point algorithms? How can I approach this. Is there somewhere I can find code for this? Thanks and regards, Abhishek If you have some algorithm for these stuff, implement a vhdl code will be easy. People of this list can give lots of h...

Hi, I'm investigating on the opportunity to switch from 93 to 2002... does any one have a link where I may find relevant informations regarding enhancements brought by 2002 ? Thanks, Vincent dude a �crit : > Hi, I'm investigating on the opportunity to switch from 93 to 2002... > does any one have a link where I may find relevant informations > regarding enhancements brought by 2002 ? > Thanks, > Vincent Hi Have a look here: http://groups.google.fr/group/comp.lang.vhdl/browse_thread/thread/3e1571a13ab8431a/9dfbd0a085f36aec?q=2002+93+nicolas&rnum=1#9dfbd0a085f36ae...

hi i would like to know how to declare the numbers in vhdl.the numbers are (2^15-1) and (-2^15). when i declare it using the REAL modelsim returns a error saying it is out of range.how to overcome it thanks hari Here an example (no problem for Modelsim) constant rl : real := 2.0**15; (remember the right operand of the power function should be an integer; so do not write 15.0. When you use the IEEE package math_real you have more functions) Egbert Molenkamp "hari" <hari_pro@yahoo.com> wrote in message news:a4a587f1.0404211903.7b799a11@posting.google.com... > hi > i...

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