VHDL switch model #2

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Dear All,
I have modified Ben Cohen's switch model code
(http://members.aol.com/vhdlcohen/vhdl/vhdlcode/switch1.vhd)
to handle multiple transactions occuring in delta times.
Could you please comment on this, are there any problems with the following
code?

Best regards,
GWJ

----------------------------------------------------------------------------
-- Copyright (c) 1997, Ben Cohen.   All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the switch model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.

-- File name  : switch1.vhd
-- Description: This entity, and architecture provide
--   the definition of a three-port component (A, B, Cab) that models a
--   transfer gate.  If Cab = '1' then A and B act as an ON switch
--   (or zero ohm connection).  Else, if Cab = '0', then A and B are
--   assigned the value of 'Z'.
--
--   The width of the pass-through switch is defined through the
--   generic "width_g".  The pass-through control and operation
--   is defined on a per bit basis (i.e. one process per bit).
--
--=================================================================
-- Design Library: User defined.
-------------------------------------------------
-- Revisions:
--   Date   Author             Revision  Comment
-- 03-31-97 Ben Cohen          Rev A     Creation
--          VhdlCohen@aol.com
-- 09-13-03 Grzegorz Jablonski Rev B     Modified to handle multiple
transactions occuring in delta times
--          gwj@dmcs.p.lodz.pl
-------------------------------------------------------------
library IEEE;
  use IEEE.Std_Logic_1164.all;

-------------------------------------------------------------
-- Entity        : Switch1
-- Purpose       : Provides interface of a component
--               : intended to be placed between signals
--               : to dynamically control faults on signals.
-- Library       : User defined
-------------------------------------------------------------
library IEEE;
  use IEEE.Std_Logic_1164.all;

entity Switch1 is
  generic (Width_g      : Positive := 32);
  port
    (A   : inout Std_Logic_Vector(Width_g - 1 downto 0) := (others => 'Z');
     B   : inout Std_Logic_Vector(Width_g - 1 downto 0) := (others => 'Z');
     Cab : in    Std_Logic_Vector(Width_g - 1 downto 0) := (others => 'Z'));
end Switch1;


--------------------------------------------------------------
-- Architecture  : Switch1_a
-- Purpose       : Implements the switch architecture.
--               : This model is optimized for speed by minimizing the
--               : number of transactions by generating one process
--               : for each element of the width for the
--               : mode of interest.
-------------------------------------------------------------
architecture Switch1_a of Switch1 is
  type StdLogic_Table is array(Std_uLogic, Std_uLogic) of Std_uLogic;

  ------------------------------------------------------------------- 
  -- resolution function, from 1164 package body
  ------------------------------------------------------------------- 
  constant Resolution_Table : Stdlogic_Table := (
  --      ---------------------------------------------------------
  --      |  U    X    0    1    Z    W    L    H    -        |   |
  --      ---------------------------------------------------------
          ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
          ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
          ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
          ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
          ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
          ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
          ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
          ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
          ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )  -- | - |
      );

  function Resolved ( S : Std_uLogic_Vector ) return Std_uLogic is
      variable Result : Std_uLogic := 'Z';  -- weakest state default
  begin
      -- the test for a single driver is essential otherwise the
      -- loop would return 'X' for a single driver of '-' and that
      -- would conflict with the value of a single driver unresolved
      -- signal.
      if    (S'length = 1) then
        return S(S'low);
      else
          for I in S'range Loop
              Result := Resolution_Table(Result, S(I));
          end loop;
      end if;
      return Result;
   end Resolved;

begin
  Px_Lbl: for I in (Width_g - 1) downto 0 generate
    ABC1_Lbl: process
      variable ThenTime_v : time;
      variable ResolvedValue_v : Std_uLogic;
   variable Cab_v : Std_Logic;
    begin
      wait on A(I)'transaction, B(I)'transaction, Cab(I)'transaction
   until (
              ThenTime_v /= now or Cab(I) /= Cab_v or
              (Cab(I) = '1' and (A(i)/=ResolvedValue_v or
B(i)/=ResolvedValue_v))
   );
      -- Break
      ThenTime_v := now;
      A(I) <= 'Z';
      B(I) <= 'Z';
      wait for 0 ns;
      Cab_v := Cab(I);
      if Cab(I) = '1' then
        -- Make.  Must compute the resolved value
        ResolvedValue_v  := Resolved((A(I), B(I)));
        A(I) <= ResolvedValue_v;
        B(I) <= ResolvedValue_v;

      else
          A(I) <= 'Z';
          B(I) <= 'Z';
      end if;
    end process ABC1_Lbl;
  end generate Px_Lbl;
end Switch1_a;


----------------------------------------------------------------------------
---
--  1 bit switch
----------------------------------------------------------------------------
---
library IEEE;
  use IEEE.Std_Logic_1164.all;

entity Switch1b is
  generic (Width_g      : Positive := 32);
  port
    (A   : inout Std_Logic := 'Z';
     B   : inout Std_Logic := 'Z';
     Cab : in    Std_Logic := 'Z');
end Switch1b;


--------------------------------------------------------------
-- Architecture  : Switch1b_a
-- Purpose       : Implements the switch architecture.
--               : This model is optimized for speed by minimizing the
--               : number of transactions by generating one process
--               : for each element of the width for the
--               : mode of interest.
-------------------------------------------------------------
architecture Switch1b_a of Switch1b is
  type StdLogic_Table is array(Std_uLogic, Std_uLogic) of Std_uLogic;

  ------------------------------------------------------------------- 
  -- resolution function
  ------------------------------------------------------------------- 
  constant Resolution_Table : Stdlogic_Table := (
  --      ---------------------------------------------------------
  --      |  U    X    0    1    Z    W    L    H    -        |   |
  --      ---------------------------------------------------------
          ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
          ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
          ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
          ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
          ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
          ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
          ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
          ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
          ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )  -- | - |
      );

  function Resolved ( S : Std_uLogic_Vector ) return Std_uLogic is
      variable Result : Std_uLogic := 'Z';  -- weakest state default
  begin
      -- the test for a single driver is essential otherwise the
      -- loop would return 'X' for a single driver of '-' and that
      -- would conflict with the value of a single driver unresolved
      -- signal.
      if    (S'length = 1) then
        return S(S'low);
      else
          for I in S'range Loop
              Result := Resolution_Table(Result, S(I));
          end loop;
      end if;
      return Result;
   end Resolved;

begin
    ABC1_Lbl: process
      variable ThenTime_v : time;
      variable ResolvedValue_v : Std_uLogic;
   variable Cab_v : Std_Logic;
    begin
      wait on A'transaction, B'transaction, Cab'transaction
   until (
              ThenTime_v /= now or Cab /= Cab_v or
              (Cab = '1' and (A/=ResolvedValue_v or B/=ResolvedValue_v))
   );
      -- Break
      ThenTime_v := now;
      A <= 'Z';
      B <= 'Z';
      wait for 0 ns;
      Cab_v := Cab;
      if Cab = '1' then
        -- Make.  Must compute the resolved value
        ResolvedValue_v  := Resolved((A, B));
        A <= ResolvedValue_v;
        B <= ResolvedValue_v;

      else
          A <= 'Z';
          B <= 'Z';
      end if;
    end process ABC1_Lbl;
end Switch1b_a;





0
Reply gwj (1) 9/13/2003 10:21:17 AM

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