VHDL switch model #2
I have modified Ben Cohen's switch model code
to handle multiple transactions occuring in delta times.
Could you please comment on this, are there any problems with the following
-- Copyright (c) 1997, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked ...Looking for a Verilog or VHDL RAM Model(or FIFO) that models RAM Faults.
Dear Gentle Persons,
Does anyone know where I could get a Verilog or VHDL RAM Model that models
common RAM Faults like Stuck At Faults on the Address, Data Lines, Stuck Ram
Cells, Coupling faults Etc?
I would also be interested in Verilog or VHDL implementation of a March SS
RAM Test, or any March type RAM Test.
check in actel's web site.
`timescale 1 ns/100 ps
// Behavioral description of FIFO with:
// active high write enable
// active high read enable
// active low asynchronous clear
// rising edge clock
// active high full flag
// active low emp...Switching between two models
I have a program that runs two models for different data sets. The first
model, that is preferred over second one, does not converge sometimes,
because number of cases is less than enough. Instead I switch to the second
model that does not have such a problem up to a point (when sample size is
very low, the second model does not converge also). When the second model
does not converge I do not want to go further. Running these models for
different data sets I have hard time in checking each model one by one to
see which is good for an especial file. So, my question is:
I...How to model a buffer in VHDL
Im trying to model a buffer in VHDL but am unable to do so...
I have a signal A and I want to generate a signal B which is nothing
but A delayed by 2 seconds.
i.e B <= A after 2 ns;
But the above way does not work as I do not see anything on B.
When A (widht of A) is high for 1ns , then B is 0 but if I increase the
width of A to 3ns then I am able to see B with a delay of 2 ns
Please suggest some way
This is because of the default ineretial delay of vhdl.To see your
required behaviour replace the inertial delay with transport delay.
b<= transport a after 20 ns;
Abila...Markov Switching Models
How to run Markov Switching Models in SAS
Thanks & Regards,
Are you refering to markov chains?
From: priyanka singh
Sender: SAS(r) Discussion
ReplyTo: priyanka singh
Subject: Markov Switching Models
Sent: Jan 22, 2010 7:57 PM
How to run Markov Switching Models in SAS
Thanks & Regards,
Sent from my BlackBerry Wireless Handheld
Certified Advanced Programmer for SAS V9
Certified Basic Programmer for SAS V9
for the simplest markov switching ...modelling a FIFO in VHDL
I am trying to send data via RS 232 to a spartan 3 development board that
has external SRAM. I want to send data to the RXD input of the FPGA and
have the FPGA send this to the SRAM. This is a simplex transmission from
my PC to the FPGA that is listening. Is there any models I can see or use
maybe for doing this kind of a UART, FIFO in VHDL ?
I assume that you have heard of the google search engine,well I suggest
you give that a try because i did and it worked for me.
...VHDL into a simulink model
Does someone know a way for transforming VHDL code into a Simulink
I'm familiar with the Simulink HDL coder, but this tool can transform
only in the opposite direction ...
Tomer Gidony wrote:
> Hi all,
> Does someone know a way for transforming VHDL code into a Simulink
> model ?
> I'm familiar with the Simulink HDL coder, but this tool can transform
> only in the opposite direction ...
The MathWorks offers a product to do exactly what you are looking for. Please see the
product page at http://www.mathworks.com/products...PCI model VHDL
could someone help me to search a free PCI model (master and target)
in VHDL language, compliant with the PCI2.2 specification?
thank you in advance.
...DDR2 VHDL model
on the following link
there are DDR2 memory VHDL simulation models from Samsung available.
But the compressed download files only contain .dat files.
Are these files suitable for functional simulations ?
I have always simulated with "real" vhdl models ...
> on the following link
>...VHDL Model for TCM3105 (Texas) ?
Hi there !
Does anybody know a model for the obsolete TCM3105 from TI ?
Thank you, Andreas.
...model pmos and nmos in VHDL
I am new to VHDL and would like to know how to model pmos and nmos in
VHDL. In verilog we use the keyword pmos and nmos. IS there an
equivalent in VHDL? Please provide an example
On 19 Jun 2006 10:51:50 -0700, firstname.lastname@example.org wrote:
> I am new to VHDL and would like to know how to model pmos and nmos in
>VHDL. In verilog we use the keyword pmos and nmos. IS there an
>equivalent in VHDL? Please provide an example
There's no direct equivalent; VHDL does not have Verilog's
Verilog's pmos and nmos are actu...VHDL Model of a stepper motor
Anybody allready designed a VHDL model of a stepper motor to simulate
in modelsim ?
On 10 Jan 2007 08:05:18 -0800, "fpgauser"
>Anybody allready designed a VHDL model of a stepper motor to simulate
>in modelsim ?
Do you really mean a model of a _stepper motor_? If so, you will
need to decide how you map from the physical properties and
operating conditions of the motor - shaft angle, externally
applied torque etc - to VHDL data types. And you will need to
decide how fast to sample and update your model in order
to mimic its co...Xilinx BlockRam: VHDL Model
i am trying to implement RAMB16_S9_S36 Block ram in Spartan IIE, which
does not support it. My aim is to utilize RAMB4_Sn_Sm in such a way to
make it a RAMB16_S9_S36, but it may have less number of address, i.e.
depth can be different than original RAMB16_S9_S36. can anyone help me
out? or someone can give me a complete VHDL model of this RAMB16_S9_S36
which must be either technology independant or at the most it must use
xilinx RAMB4_Sn_Sm ram. Thanks
> i am trying to implement RAMB16_S9_S36 Block ram in Spartan IIE, which
> does not support it. My aim is to ...VHDL switch in real numbers
does anyone know if it would be possible to implement an "analog" (real
number) version of Ben Cohen's bidirectional switch in VHDL?
> does anyone know if it would be possible to implement an "analog"
> (real number) version of Ben Cohen's bidirectional switch in VHDL?
You mean http://members.aol.com/vhdlcohen/vhdl/vhdlcode/switch1.vhd ?
And do you mean replacing the std_logic types with reals?
That cannot be done, as the types of the A and B ports must be
resolved types. You could create your o...cisco switch / router model???
i'll need to setup the following connection:
Vlan1 and Vlan2<---[main site]<---100 FastEthernet-->[remote site]----
>Vlan1 and Vlan2
Vlan1 and Vlan2 will connect back to their own network by using the
100 FE line.
in order to keep at a reasonable cost, which model of cisco switch or
router should i use for main site and remote site?
...micron vhdl models gone ??
I'am having troubles finding the VHDL models on the micron site. Do others
have the same problem?
Mit freundlichen Gr�ssen
P.S. Achtung wir haben eine neue FAX-Nummer
** Meng Engineering Telefon 056 222 44 10 **
** Markus Meng Natel 079 230 93 86 **
** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! **
** CH-5400 Baden Email email@example.com **
** Web www.meng...VHDL models for DDR2 SDRAM?
Can someone please recommend some VHDL DDR2 SDRAM models?
Specifically, I'm targetting a MT47H64M16 part. I've tried using an
open source model from the "Free Model Foundry," but it's buggy and
doesn't support seamless writes. Micron doesn't seem to be publishing
free VHDL models anymore (only Verilog). We run a VHDL shop and
don't even have Verilog/Mixed licenses for our simulator.
Does anyone have any suggestions? I've started looking into Denali.
The functionality is impressive, but seems a bit "overkill" for this
application. I just ne...VHDL NAND flash model
Has anyone on the board seen a VHDL version of NAND flash?
Looking on the various NAND flash vendor websites I can see Verilog
models, but I haven't seen a VHDL model from any of them.
I'm looking to start a pet project of a NAND flash controller to
release on opencores.org.
There are models of Spansion NAND interface NOR flash on the FMF site
> Has anyone on the board seen a VHDL version of NAND flash?
> Looking on the various NAND flash vendor websites I can see Verilog
> models, but I haven't seen a VHDL model from ...VHDL modelling USB device
Hi VHDL folks,
does somebody know if there are VHDL models available for
USB devices ? A simple model (behavioral) would do the
Any hints are appreciated.
Thank you for your help.
>Hi VHDL folks,
>does somebody know if there are VHDL models available for
>USB devices ? A simple model (behavioral) would do the
>Any hints are appreciated.
>Thank you for your help.
Thomas Rudloff <thomasREMOVE_rudloffREMOVE@gmx.net> wrote in message news:<41...Cheapest Cisco switch model.
I must put it behind a 877 that manages VLANS. The office has 15-20 PCs on 1 VLAN and 3 on the other one.
Basically we only need VLANs.
And obviously I would like to backup the configuration remotely (for that reason I'll choose Cisco)
1. Catalyst Express 500 - but does not use Cisco CLI but a GUI instead
Approx $600 USD)
2. Catalyst 2960 ( approx $700-$885 - shop around)
So since you have an 877 that use the IOS CLI you are propably better
off trying to get a 2960 or a used 2950 that has been relicensed
...Upgrading to Gb switch... which model?
I currently have a 48 port 100Mbps Cisco switch and am looking to
upgrade to a Gb model, also with 48 ports. I don't need Layer 3 and
in looking at some sites it looks as though they have relevant models
ranging from $2000 - $5000. Can anybody recommend a basic model from
Cisco I should look at, or something similar from another company that
is a good bit cheaper yet just as reliable? I checked out extreme but
they didn't seem to have any 48 port Gb 1U models. I do need it to be
1U in size, don't know if that is something that is Cisco only.
Also, I saw a few models with SFP po...Switched Reluctance Motor Model
Please Someone Help me to model and simulate a SRM with its driver
Ehab Elwakil wrote:
> Please Someone Help me to model and simulate a SRM with its driver
i can help u
> Ehab Elwakil wrote:
>> Please Someone Help me to and simulate a SRM with its
> i can help u
> mailme back
> can ur also help me how to and simulate SRM with
in the new version of simulink they have added an SRM model in the
Ehab Elwakil wrote:
...Multivariate Markov-Switching Models
Does anyone knows if SAS can estimate Multivariate Markov-Switching
Models, i.e., a VAR model with regime switch?
Usually, the EM algorithm is used to estimate the model.
>Does anyone knows if SAS can estimate Multivariate Markov-Switching
>Models, i.e., a VAR model with regime switch?
>Usually, the EM algorithm is used to estimate the model.
Actually, I'm not sure. I've never tried doing this in PROC VARMAX,
but that would be where I started looking. PROC VARMAX will do
bo...System ACE VHDL Model
I'm currently working on a interface to a CF-Card via a System ACE
I was wondering if somebody already did a create a "Model" of a System
ACE Controller to use it in some testbenches to verify the interface
is working correctly?
On Jul 14, 4:36=A0pm, AndreasWallner <Andreas.Wallner.et...@fh-
> I'm currently working on a interface to a CF-Card via a System ACE
> I was wondering if somebody already did a create a "Model" of a System
> ACE Controller to use it in some ...