All,

The readers on this newsgroup may be interested in this Intel positioning p=
aper
comparing Itanium and x86 RAS:

http://tinyurl.com/6h3n87 (see Appendix A)

original link  (may wrap)
http://download.intel.com/products/processor/itanium/RAS_WPaper_Final_1207.=
pdf



Regards

Kerry Main
Senior Consultant
HP Services Canada
Voice: 613-254-8911
Fax: 613-591-4477
kerryDOTmainAThpDOTcom
(remove the DOT's and AT)

OpenVMS - the secure, multi-site OS that just works.

On Fri, 18 Apr 2008 16:02:41 -0700, Main, Kerry <Kerry.Main@hp.com> wrote:

I know it isn't Row Address Strobe.  Usually I can decode the acronym
 from the context, but this one has me stumped, guess I am getting dumb.

"
Mainframe-Class RAS in the Processor
The Intel Itanium processor was designed from its inception to
deliver mainframe-class availability. It incorporates leading RAS
capabilities for detecting, correcting and containing the kinds of
unavoidable hard and soft errors that can bring down systems or
corrupt data (Table 1 on next page).
"

I discovered I couldn't cut and paste the above quote from Opera, but
Firefox let me, FWIW.
-- 
PL/I for OpenVMS
www.kednos.com

In article <op.t9uzkzwuhv4qyg@murphus.hsd1.ca.comcast.net>,
 "Tom Linden" <tom@kednos.company> wrote:

> On Fri, 18 Apr 2008 16:02:41 -0700, Main, Kerry <Kerry.Main@hp.com> wrote:
> 
> I know it isn't Row Address Strobe.  Usually I can decode the acronym
>  from the context, but this one has me stumped, guess I am getting dumb.
> 
> "
> Mainframe-Class RAS in the Processor
> The Intel Itanium processor was designed from its inception to
> deliver mainframe-class availability. It incorporates leading RAS
> capabilities for detecting, correcting and containing the kinds of
> unavoidable hard and soft errors that can bring down systems or
> corrupt data (Table 1 on next page).
> "
> 
> I discovered I couldn't cut and paste the above quote from Opera, but
> Firefox let me, FWIW.

I'm 99% sure they are referring to this meaning of RAS (and not Remote 
Access Server):

<http://www.intel.com/business/bss/products/server/ras.pdf>

"Reliability, Availability, and Serviceability for the Always-on 
Enterprise"

-- 
Paul Sture

Sue's OpenVMS bookmarks:
http://eisner.encompasserve.org/~sture/ovms-bookmarks.html

On Apr 19, 1:56 pm, "Tom Linden" <t...@kednos.company> wrote:
> On Fri, 18 Apr 2008 16:02:41 -0700, Main, Kerry <Kerry.M...@hp.com> wrote:
>
> I know it isn't Row Address Strobe.  Usually I can decode the acronym
>  from the context, but this one has me stumped, guess I am getting dumb.
>
> "
> Mainframe-Class RAS in the Processor
> The Intel Itanium processor was designed from its inception to
> deliver mainframe-class availability. It incorporates leading RAS
> capabilities for detecting, correcting and containing the kinds of
> unavoidable hard and soft errors that can bring down systems or
> corrupt data (Table 1 on next page).
> "
>
> I discovered I couldn't cut and paste the above quote from Opera, but
> Firefox let me, FWIW.
> --
> PL/I for OpenVMSwww.kednos.com

In this context, RAS usually decodes to something like Reliability,
Availability, Serviceability.

I haven't had a proper look at the paper yet. What I did note from a
quick look was that it seemed heavy on benefits and handwaving, light
on real features required to provide real benefits - other than
largely-irrelevant core lockstep, the "two bit" thing is the only
feature I remember reading about. Some of the features/benefits seemed
more like OS kind of things (is "page poisoning" a hardware feature or
something any half-decent OS does for you?). Hopefully later in the
week I'll be back.

The other point to note is that, despite their recent delivery issues,
the real technical competitor to Itanium is imo AMD64. AMD64 and Xeon
may have mostly the same instruction set, but my reading of the AMD64
architecture and current implementations is that they seem, shalll we
say, less legacy-bound than Xeon. CSI (or whatever it's called this
week) may reduce some of that gap, perhaps.

2c
John