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[dasip-2] CfP Extended Deadline May 14> DASIP Conference > October 23-25, Karlsruhe, Germany #2

[http://www.ecsi.org/sites/default/files/images/DASIP%20LOGO_257x73px.jpg]<h
ttp://www.ecsi.org/dasip>
The 2012 Conference
on Design and Architectures
for Signal and Image Processing
Karlsruhe, Germany
October 23-25, 2012
Call for Contributions
Extended Deadline May 14!
Last Reminder!
General Co-Chairs:
Michael H�bner, Ruhr-Universit�t Bochum, Germany
Daniel Chillet, Universit� de Rennes 1, France

www.ecsi.org/dasip

DASIP 2012 is organized with the technical co-sponsorship
of the IEEE Signal Processing Society.
[http://www.ecsi.org/sites/default/files/images/IEEE.gif]
[http://www.ecsi.org/sites/default/files/images/Logo_SPS_small3.jpg]

Description
The DASIP Organization Committee and ECSI are pleased to invite you to the
Design and Architectures for Signal and Image Processing (DASIP) 2012
Conference that will take place in Karlsruhe, Germany, October 23-25. The
goals of DASIP are to present the latest results in the domain of design and
architecture for signal, communication and image processing and to provide
to researcher and industry community a reference exchange platform
addressing this topic. The conference program includes keynote speeches,
contributed paper sessions, poster sessions and demonstrations. Prospective
authors are invited to submit manuscripts on topics including, but not
limited to:
Design Methods and Tools
Design verification and fault tolerance
Embedded system security and security validation
System-level design and hardware/software co-design
Communication synthesis, architectural and logic synthesis
Embedded real-time systems and real-time operating systems
Rapid system prototyping, performance analysis and estimation
Formal models, transformations, algorithm transformations and metrics
Development Platforms, Architectures and Technologies
Embedded platforms for multimedia and telecom
Many-core and multi-processor systems, SoCs, and NoCs
Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
Asynchronous (self-timed) circuits and analog and mixed-signal circuits
Digital bio-signal processing, biologically based and/or inspired systems
Use-Cases and Applications
Ambient intelligence, ubiquitous and wearable computing
Global navigation satellite systems, smart cameras, and PDAs
Security systems, cryptography, object recognition and tracking
Embedded systems for automotive, aerospace, and health applications
Smart Sensing Systems
Sensor networks, environmental and system monitoring
Vision, audio, fingerprint, health monitoring, and biosensors
Structurally-embedded, distributed, and multiplexed sensors
Sensing for active control systems, adaptive and evolutionary sensors

Special Sessions

DASIP 2012 will feature eight Special Sessions that will run throughout the
conference. These Special Sessions have the purpose of introducing the DASIP
community to relevant hot topics that were not sufficiently covered by
previous editions of the conference.

This call is an invitation for scientists and professionals to submit
manuscripts for Special Sessions for DASIP 2012. Prospective authors are
invited to submit manuscripts on the following topics:
Architectures for Forward Error Correction Decoders
Co-Chairs: Matthieu Arzel, Telecom Bretagne, FR & Camille Leroux,
Enseirb-Matmeca, FR
Arithmetic for Image and Signal Processing
Co-Chairs: Gabriel Caffarena, U. CEU San Pablo, ES & Daniel Menard, U. of
Rennes 1, FR
Biomedical Systems and Devices
Co-Chairs: Olivier Romain, ENSEA, FR & Patrick Garda, UPMC, FR
Embedded Operating Systems for Signal Processing Applications
Co-Chairs: Jalil Boukhobza & Jean Philippe Babau, U. of Occidental Britanny,
FR,
& John Williams, U. of Queensland, AU
Methods and Tools Based on Dataflow Programming
Co-Chairs: Johan Lilius, Abo University, FI & Jean Fran�ois Nezan, INSA
Rennes, FR
Pulse Processing
Co-Chairs: Mathieu Thevenin, CEA, FR & Gwenol� Corre, CEA, FR
Reconfigurable Systems and Tools for Signal and Image Processing
Co-Chairs: Diana G�hringer, Fraunhofer IOSB, DE, Juanjo Noguera, Xilinx, IE,
Sebastien Pillement, U. of Rennes 1, FR
Visual Surveillance
Co-Chairs: Marek Gorgon, U. of AGH, PL &  Walter Stechele, TUM, DE

Submission Requirements
Authors should submit their full papers (up to 8 pages, double-column IEEE
format) in PDF through the web based submission system. Proceedings of DASIP
2012 will be included in the IEEE Xplore Digital Library. Submitted papers
should be anonymous, are required to describe original unpublished work and
must not be under consideration for publication elsewhere. After the
conference, papers and presentations will be published on the ECSI website
together with the keynote presentations (subject to confidentiality issues).
Authors of the best papers will be invited to submit an extended version of
their work to the International Journal of Real-Time Image Processing
(IJRTIP), in which a special issue on DASIP will be published in the third
quarter of 2012. The selected best papers from several DASIP editions will
be published in a book edited by SPRINGER.
Submission requirement details can be found at
www.ecsi.org/dasip<http://www.ecsi.org/dasip> .

Important Dates

Paper submission deadline:

Notification of acceptance:

Camera ready papers:


April 30, 2012 May 14, 2012 (extended)
June 25, 2012
September 17, 2012


Organizing Committee
General Co-Chairs:
Michael H�bner, Ruhr-Universit�t Bochum, Germany
Daniel Chillet, Universit� de Rennes 1, France
Program Co-Chairs:
Paolo Meloni, University of Cagliari, Italy
Christophe Jego, Bordeaux Institute of Technology, France
Local Coordinators:
Gabriel Marchesan Almeida, Karlsruhe Institute of Technology, Germany
Diana G�hringer, Fraunhofer IOSB, Germany
Technical Program Committee
Mohamed Abid, CES Laboratory, TN
Matthieu Arzel, Telecom Bretagne, FR
Jean Philippe Babau, U. of Occidental Britanny, FR
Iuliana Bacivarov, ETH Zurich, CH
Shailendra Baraniya, NMIMS University, IN
Cecile Belleudy, University Nice Sophia Antopilis, FR
Mladen Berekovic, Technical University of Braunschweig, DE
Christophe Bobda, University of Arkansas, US
Jalil Boukhobza, U. of Occidental Britanny, FR
Ahmed Bouridane, Northumbria University Newcastle, GB
Jani Boutellier, University of Oulu, FI
Giovanni Busonera, CRS4, IT
Joan Cabestany, Universitat Polit�cnica Catalunya UPC, ES
Gabriel Caffarena, U. CEU San Pablo, ES
Jo�o Cardoso, Universidade do Porto, FEUP, PT
Emmanuel Casseau, Universit� de Rennes 1 FR
St�phane Chevobbe, CEA LIST FR
Daniel Chillet, ENSSAT, FR
Christopher Claus, Robert Bosch GmbH DE
Gwenol� Corre, CEA, FR
Milos Drutarovsky, Technical University of Kosice, SK
Marc Duranton, CEA, FR
Ahmet Erdogan, University of Edinburgh, GB
Carles Ferrer, UAB, ES
Alberto Garcia-Ortiz, U.Bremen / ITEM DE
Patrick Garda, Universit� Pierre et Marie Curie, FR
Guy Gogniat, Universit� de Bretagne Sud, FR
Diana G�hringer, Karlsruhe Institute of Technology, DE
Marek Gorgon, U. of AGH, PL
Bertrand Granado, ENSEA, FR
Arnaud Grasset, Thales Research & Technology, FR
Frank Hannig, University of Erlangen-Nuremberg, DE
Dominique Houzet, GIPSA-Lab, FR
Gareth Howells, University of Kent, UK
Michael Huebner, Karlsruihe Institute of Technology (KIT) DE
Jorn Janneck, Lund University, SE
Christophe Jego, Institut Polytechnique de Bordeaux FR
Nathalie Julien, Lab-STICC Lorient FR
Udo Kebschull, Goethe-University Frankfurt, DE
Peter Koch, Aalborg University, DK
Ouassila Labbani-Narsis, University of Burgundy FR
Johann Laurent, Lab-STICC, FR
Yannick Le Moullec, Aalborg University, DK
Jean-Didier Legat, Universit� catholique de Louvain BE
Camille Leroux, Enseirb-Matmeca, FR
Shujun Li, University of Surrey, UK
Johan Lilius, Abo University, FI
Yuzhe Liu, University of Notre Dame, US
Felix Lustenberger, LUTECO Lustenberger Technology Consulting CH
St�phane Mancini, TIMA laboratory FR
Philippe Manet, Universit� Catholique de Louvain BE
Marco Mattavelli, EPFL, CH
Klaus McDonald-Maier, University of Essex, UK
Samy Meftali, Universit� de Lille 1 - INRIA FR
Paolo Meloni, University of Cagliari, IT
Daniel Menard, U. of Rennes 1, FR
Beno�t Miramond, ETIS FR
Adam Morawiec,  ECSI, FR
Jean Fran�ois Nezan, INSA IETR, FR
Smail Niar, University of Valenciennes FR
Juanjo Noguera, Xilinx, IE
Tokunbo Ogunfunmi, Santa Clara University US
Michel Paindavoine, University of Burgundy - LEAD, FR
Vassilis Paliouras, University of Patras, GR
Francesca Palumbo, University of Cagliari IT
Danilo Pani, DIEE - University of Cagliari, IT
Sebastien Pillement, University of Rennes 1 / IRISA, FR
Mickael Raulet, IETR/INSA Rennes, FR
Frederic Robert, Universite libre de Bruxelles, BE
Olivier Romain, ENSEA, FR
Gilles Sassatelli, LIRMM - CNRS / University of Montpellier II FR
Simone Secchi, Pacific Northwest National Laborator US
Eric Senn, Universit� de Bretagne Sud, FR
M. Shawky, Heudiasyc, UTC, FR
Gilles Sicard, TIMA Laboratory - UJF - Grenoble, FR
Yves Sorel, INRIA Rocquencourt FR
Dimitrios Soudris, National Technical Univ. of Athen, GR
Walter Stechele, TUM, DE
Jarmo Takala, Tampere University of Technology, FI
Mathieu Thevenin, CEA FR
Arnaud Tisserand, CNRS-IRISA FR
Fran�ois Verdier, LEAT, FR
Nikolaos Voros, Technological Educational Institute of Mesolonghi, GR
Serge Weber, Lorraine University, FR
John Williams, U. of Queensland, AU
Matthieu Wipliez, Synflow, FR
Olivier Zendra, INRIA, FR
LOCAL ORGANIZER
Karlsruhe Institute of Technology, Germany
SECRETARIAT
ECSI Office
office@ecsi.org
dasip2012@ecsi.org
Ph: +33 4 76 63 49 34
Fax: +33 9 58 08 24 13

DASIP Demo Night
This year, for the 1st time, a special evening event is organized during
DASIP: the DASIP Demo Night, Tuesday, October 23, 2012, from 7:00pm up to
9:30pm.
The goal of this event is to present collaborative projects and to show
demonstrations (hardware platforms, prototypes, design frameworks,
tools,...).
A dedicated space in a large room will be devoted to each demo such that one
or two posters can be used jointly with the demo.
DASIP Demo Night makes it ideal to discussions and start new collaborations.
A buffet dinner will take place during this event to make it friendly.
Submissions should be send by Monday, July 2, 2012 (through the web based
submission system) :
-    Format : 2 page length, double-column IEEE format
-    Title of the project/demo
-    List of the partners
-    Short abstract: it will be included in the Demo Night program. Should
not exceed 5 lines
-    Extended abstract
-    The submission will be processed in a peer review process
-    After acceptance, the paper will be included into the proceedings of
DASIP
Demo night important dates:
Paper submission deadline

July 2, 2012

Notification of acceptance

August 30, 2012

Camera ready papers

September 17, 2012

Demo night event

October 23, 2012, 7:00pm-9:30pm


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[http://www.ecsi.org/sites/default/files/images/S4D%20logo%20small.jpg] <http://www.ecsi.org/s4d> System, Software, SoC and Silicon Debug Conference September 19-20, 2012 Vienna, Austria Call for Contributions Deadline April 23! Chair: Peter R�ssler, University of Applied Sciences Technikum Wien www.ecsi.org/s4d Description Embedded systems and software complexity is rapidly increasing; from one processor to ten or more, from thousands of lines of code to millions. Modern system-on-chips integrate dozens of hardware accelerators and I/O devices. Modern products integrate hard IP and software from many more sources than in the recent past. Embedded systems debug capabilities must scale with this exponential growth in system complexity. This fourth edition of S4D Conference has evolved from several industry workshops organized by ECSI into the areas of debug and provides a forum for work and standardization efforts related to debug of electronic systems. The conference addresses a vast set of requirements from system and SoC companies with regard to debug methods and tools. It includes efforts from IEEE and other standards working groups, including the Nexus 5001 Forum, IJTAG (IEEE P1687), IEEE 1149.7, MIPI, industry working groups including OCP-IP, the Multicore Association (MCA), the Accellera - SPIRIT Consortium and Eclipse and industry R&D projects contributing to debug and related tools and methods development. The S4D Conference event also allows presentatio...

[s4d-2] CfP Extended Deadline May 7 > S4D Conference > Sept 19-20, Vienna, Austria
[http://www.ecsi.org/sites/default/files/images/S4D%20logo%20small.jpg] <http://www.ecsi.org/s4d> System, Software, SoC and Silicon Debug Conference September 19-20, 2012 Vienna, Austria Call for Contributions Extended Deadline May 7! Chair: Peter R�ssler, University of Applied Sciences Technikum Wien www.ecsi.org/s4d S4D is organized with the technical co-sponsorship of IEEE Austria Section [http://www.ecsi.org/sites/default/files/images/IEEE.gif] [http://www.ecsi.org/sites/default/files/images/IEEE_Austria_Logo.png] Description Embedded systems and software complexity is rapidly increasing; from one processor to ten or more, from thousands of lines of code to millions. Modern system-on-chips integrate dozens of hardware accelerators and I/O devices. Modern products integrate hard IP and software from many more sources than in the recent past. Embedded systems debug capabilities must scale with this exponential growth in system complexity. This fourth edition of S4D Conference has evolved from several industry workshops organized by ECSI into the areas of debug and provides a forum for work and standardization efforts related to debug of electronic systems. The conference addresses a vast set of requirements from system and SoC companies with regard to debug methods and tools. It includes efforts from IEEE and other standards working groups, including the Nexus 5001 Forum, IJTAG (IEEE P1687), IEEE 1149.7, MIPI, industry working groups including OCP-IP, the Multico...

[ecsi-2] CfP Deadline March 23 > ESLsyn-Electronic System Level Synthesis Conference > June 2-3, San Francisco, CA
[http://www.ecsi.org/sites/default/files/images/ESLsyn-small.jpg]<http://www ..ecsi.org/eslsyn> Electronic System Level Synthesis Conference June 2-3, 2012 San Francisco, California, USA General Co-Chairs: Sandeep K. Shukla, Virginia Tech, US & Philippe Coussy, Lab-STICC, FR Program Co-Chairs: Jens Brandt, TU Kaiserslautern, DE & Achim Rettberg, U. of Oldenburg, DE Organization Chair: Adam Morawiec, ECSI, FR www.ecsi.org/eslsyn ESLsyn is organized with the technical co-sponsorship of IEEE & IEEE Council on Electronic Design Automation (CEDA) [http://www.ecsi.org/sites/default/files/images/IEEE.gif] [http://www.ecsi.org/sites/default/files/images/CEDA_Logo_small2.jpg] Description The ever-increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementations are needed for designing both HW and SW parts. ESL design does not only provide system architects with the right tools to make the right decisions about the system architecture, it includes the methodologies and techniques that correlate the ESL model. A well-connected ESL-to-implementation design flow is needed. The system design teams expect newer and more efficient methods and tools supporting better management of the design complexity and reduction of the design cyc...

[ecsi-2] CfP Deadline April 13 (extended) > ESLsyn-Electronic System Level Synthesis Conference > June 2-3, San Francisco, CA
[http://www.ecsi.org//sites/default/files/images/ESLsyn-small.jpg]<http://ww w.ecsi.org/eslsyn> Electronic System Level Synthesis Conference Call for Contributions Extended deadline! Abstract submission deadline: April 13 Paper submission deadline: April 16 June 2-3, 2012 San Francisco, California, USA General Co-Chairs: Sandeep K. Shukla, Virginia Tech, US & Philippe Coussy, Lab-STICC, FR Program Co-Chairs: Jens Brandt, TU Kaiserslautern, DE & Achim Rettberg, U. of Oldenburg, DE Organization Chair: Adam Morawiec, ECSI, FR www.ecsi.org/eslsyn ESLsyn is organized with the technical co-sponsorship of the IEEE Council on Electronic Design Automation (CEDA) [http://www.ecsi.org/sites/default/files/images/IEEE.gif] [http://www.ecsi.org/sites/default/files/images/CEDA_Logo_small2.jpg] Description The ever-increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementations are needed for designing both HW and SW parts. ESL design does not only provide system architects with the right tools to make the right decisions about the system architecture, it includes the methodologies and techniques that correlate the ESL model. A well-connected ESL-to-implementation design flow is needed. The system design teams expect newer and more ef...

[s4d-2] CfP Deadline April 23 > S4D Conference > Sept 19-20, Vienna, Austria
[http://www.ecsi.org/sites/default/files/images/S4D%20logo%20small.jpg] <http://www.ecsi.org/s4d> System, Software, SoC and Silicon Debug Conference September 19-20, 2012 Vienna, Austria Call for Contributions Deadline April 23! Chair: Peter R�ssler, University of Applied Sciences Technikum Wien www.ecsi.org/s4d Description Embedded systems and software complexity is rapidly increasing; from one processor to ten or more, from thousands of lines of code to millions. Modern system-on-chips integrate dozens of hardware accelerators and I/O devices. Modern products integrate hard IP and software from many more sources than in the recent past. Embedded systems debug capabilities must scale with this exponential growth in system complexity. This fourth edition of S4D Conference has evolved from several industry workshops organized by ECSI into the areas of debug and provides a forum for work and standardization efforts related to debug of electronic systems. The conference addresses a vast set of requirements from system and SoC companies with regard to debug methods and tools. It includes efforts from IEEE and other standards working groups, including the Nexus 5001 Forum, IJTAG (IEEE P1687), IEEE 1149.7, MIPI, industry working groups including OCP-IP, the Multicore Association (MCA), the Accellera - SPIRIT Consortium and Eclipse and industry R&D projects contributing to debug and related tools and methods development. The S4D Conference event also allows presentatio...

CfP extended deadline: May 16! > (DASIP) Conference on Design & Architectures for Signal & Image Processing
[http://www.ecsi.org/sites/default/files/images/DASIP%20LOGO_257x73px.jpg] <http://www.ecsi.org/dasip> The 2011 Conference on Design and Architectures for Signal and Image Processing Tampere, Finland November 2 - 4, 2011 Call for Contributions Extended Deadline: May 16, 2011 General Chairs: Tapani Ahonen and Jari Nurmi Tampere University of Technology, Finland www.ecsi.org/dasip DASIP2011 is organized with the technical co-sponsorship of IEEE and the IEEE Signal Processing Society. [http://www.ecsi.org/sites/default/files/images/IEEE.gif] [http://www.ecsi.org/sites/default/files/images/Logo_SPS_small3.jpg] Description The DASIP Organization Committee and ECSI are pleased to invite you to the Design and Architectures for Signal and Image Processing (DASIP) 2011 Conference that will take place in Tampere, Finland, a city known for its industrial history and technological leadership from November 2-4, 2011. The goals of DASIP are to present the latest results in the domain of design and architecture for signal, communication and image processing and to provide to researcher and industry community a reference exchange platform addressing this topic. The conference program includes keynote speeches, contributed paper sessions, poster sessions and demonstrations. Prospective authors are invited to submit manuscripts on topics including, but not limited to: Design Methods and Tools � Design verification and fault tolerance � Embedded system security and s...

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[fdl-2] CfP Deadline April 2 > FDL-Forum on specification & Design Languages > Vienna, Austria > Sept 18-20, 2012
[http://www.ecsi.org/sites/default/files/images/FDL%20logo%20203x73px.jpg]<http://www.ecsi.org/fdl> Call for Contributions Deadline April 2! FDL2012 Forum on specification & Design Languages Vienna, Austria September 18-20, 2012 Conference Chair: Jan Haase, TU Vienna www.ecsi.org/fdl FDL 2012 is organized with the technical co-sponsorship of IEEE Austria Section [http://www.ecsi.org/sites/default/files/images/IEEE.gif] [http://www.ecsi.org/sites/default/files/images/IEEE_Austria_Logo.png] Description FDL is an international forum to exchange experiences and promote new trends in the application of languages, their associated design methods and tools for the design of electronic systems. The Forum is organized around four Thematic Areas (TA) described below and includes working sessions, poster sessions, embedded tutorials, panels and technical discussions. Industrial Workshops and Fringe Meetings such as user group or standardization meetings are also held in conjunction with the Forum. Technical Areas 1. ABD TA: Assertion Based Design, Verification & Debug TA Chair: Dominique Borrione (Dominique.Borrione@imag.fr) ABD TA Description: The ABD Thematic Area welcomes research contributions, tool demonstrations, reports on standardization activities and effective applications in all aspects of innovative property expression and processing, with an emphasis on frontier design levels, verification, automatic synthesis and mechanized debug aids. The assertion of fo...

[ecsi-2] ESLsyn > Call for Papers extended deadline March 12 > Electronic System Level Synthesis Conference > co-located with DAC!
[http://www.ecsi.org//sites/default/files/images/ESLsyn_200x63.jpg] <http:= //www.ecsi.org/eslsyn> ESLsyn May 31 - June 1, 2013 Austin, TX, USA Co-located with DAC! General Chair Achim Rettberg, University of Oldenburg, Germany Call for Contributions Extended Paper Submission Deadline:February 26, 2013 March 12, 2013 Description The ever-increasing need for enhanced productivity in designing highly comp= lex electronic systems drives the evolution of design methods beyond tradit= ional approaches. Virtual prototyping, design space exploration and system = synthesis are needed to design optimized systems, comprising hardware and s= oftware implementations. Electronic system-level (ESL) design promises to p= rovide system architects with the right tools to make the right decisions a= bout the system architecture at early stages of the design process. This in= cludes methodologies and synthesis techniques that are supported by appropr= iate ESL models. Furthermore, a well-connected ESL-to-implementation design= flow is needed. Overall, designing at higher levels of abstraction coupled= with the right tool support is a viable way to better cope with the system= design complexity, by increasing code reuse and allowing components to be = verified earlier in the design process. The Electronic System Level Synthesis Conference ESLsyn focuses on automate= d system design methods that enable efficient modelling, synthesis, explora= tion a...

Help construct a tree 1 -> 1.1 -> 1.2 -> 2 -> 2.1 -> 2.1.1 etc HELP !!!!!!!
Borland Guru's I need help I have a text file as follows: 1 2 1.1 1.1.1 3.3 2.3 etc I cannot use a control active x tree I need to read this file and 1 is a parent 1.1 is a child of parent 1 and 2 is a parent 2.3 is a child of parent 2 and construct in search a way using arrays or probably a recursive function No xml parsing just read a file. Does any body have a function "Mos" <lndebug@gmail.com> wrote in message news:c1aaeb20-3c1f-408d-9986-bb8d28a87509@s31g2000vbp.googlegroups.com... > I have a text file as follows: > 1 > 2 > 1.1 >...

Help construct a tree 1 -> 1.1 -> 1.2 -> 2 -> 2.1 -> 2.1.1 etc HELP !!!!!!!
Folks I need help. I have a view or(Text file) as follows: '1 2.1 1.1.1 1.1.1.1 2.2.1 1.3 2 Dim Parent() As String Dim Level1() As String Dim Level2() As String Dim Level3() As String etc .. How can I construct a tree. parent, children, grand children etc... and also figure out # of children # of grand children etc Thanks "Mos" <lndebug@gmail.com> wrote in message news:875cd1df-7605-45ab-9f7b-f1edec25d47b@r34g2000vbi.googlegroups.com... > Folks I need help. I have a view or(Text file) as follows: > > '1 > 2.1 > 1.1.1 > 1....

Help construct a tree 1 -> 1.1 -> 1.2 -> 2 -> 2.1 -> 2.1.1 etc HELP !!!!!!!
Folks I need help. I have a view or(Text file) as follows: '1 2.1 1.1.1 1.1.1.1 2.2.1 1.3 2 Dim Parent() As String Dim Level1() As String Dim Level2() As String Dim Level3() As String etc .. How can I construct a tree. parent, children, grand children etc... and also figure out # of children # of grand children etc Thanks "Mos" <lndebug@gmail.com> wrote in message news:875cd1df-7605-45ab-9f7b-f1edec25d47b@r34g2000vbi.googlegroups.com... > Folks I need help. I have a view or(Text file) as follows: > > '1 > 2.1 > 1.1.1 > 1....

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Web resources about - [dasip-2] CfP Extended Deadline May 14> DASIP Conference > October 23-25, Karlsruhe, Germany #2 - comp.parallel

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