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[ecsi-2] ESLsyn Conference > Register now! > June 2-3, San Francisco, Co-located with DAC

[http://www.ecsi.org/sites/default/files/images/ESLsyn-small.jpg]<http://www
..ecsi.org/eslsyn>
Electronic System Level Synthesis Conference
Register now! <http://www.ecsi.org/eslsyn2012/registration>
June 2-3, 2012
San Francisco, California, USA
General Co-Chairs:
Sandeep K. Shukla, Virginia Tech, US & Philippe Coussy, Lab-STICC, FR
Program Co-Chairs:
Jens Brandt, TU Kaiserslautern, DE & Achim Rettberg, U. of Oldenburg, DE
Organization Chair: Adam Morawiec, ECSI, FR

www.ecsi.org/eslsyn

ESLsyn is organized with the technical co-sponsorship
of IEEE & IEEE Council on Electronic Design Automation (CEDA)
[http://www.ecsi.org/sites/default/files/images/IEEE.gif]
[http://www.ecsi.org/sites/default/files/images/CEDA_Logo_small2.jpg]


Program

SATURDAY, JUNE 2

09:00  KEYNOTE 1: Stephen Edwards, Columbia University

From Recursive Functions to Real FPGAs

10:00  INVITED PRESENTATION: Michael McNamara, Cadence

Deploying High-Level Synthesis for Production Design: Hurdles and Hopes

11:00  SESSION 1: HIGH-LEVEL SYNTHESIS

Trimmed VLIW: Moving Application Specific Processors Towards High Level
Synthesis
Janarbek Matai, Jason Oberg, Ali Irturk, Ryan Kastner (University of
California, San Diego), and Taemin Kim (Intel)

A Model-Based Inter-Process Resource Sharing Approach for High-Level
Synthesis of Dataflow Graphs
Christian Zebelein and Christian Haubelt (University of Rostock), Joachim
Falk and Christian Haubelt (University of Erlangen-Nuremberg)

13:00  INVITED PRESENTATION

14:00  SESSION 2: MODELLING

Synthesizing Embedded Software with Safety Wrappers through Polyhedral
Analysis in a Polychronous Framework
Mahesh Nanjundappa, Matthew Kracht, Julien Ouy and Sandeep Shukla (Virginia
Tech)

Automatic Generation of Observers from MARTE/CCSL
Fr�d�ric Mallet (Universit� Nice-Sophia Antipolis)

15:15  INVITED PRESENTATION: Arkadeb Ghosal, National Instruments

System Level Modeling, Analysis and Synthesis for Domain Specific
Applications

16:15  DEMO SESSION

Demonstrators Include:
National Instruments Lab at Berkeley
Cadence
Forte DS
COMPLEX Project

18:00 SOCIAL EVENT  Buca di Beppo

SUNDAY, JUNE 3

09:00  KEYNOTE 2: Satnam Singh, Google

A Fresh Look at High Level Synthesis

10:00  KEYNOTE 3: John Sanguinetti, Forte DS

High-level Synthesis: Where We Are and How We Got Here

11:15  SPECIAL SESSION

Achim Rettberg, University of Oldenburg

Vittorio Zaccaria, PoliMi

Franco Fummi, University of Verona
Enabling Tools for Virtual Platforms

13:15  KEYNOTE 4: Benjamin Carrion Schafer, NEC

Challenges and Opportunities of Behavioral Level SoC Design

14:15  SESSION 3: HIGH-LEVEL SYNTHESIS

High-level Synthesis with Multi-Cycles Chaining and Behavior-level Timing
Extraction
Hongbin Zheng, Qingrui Liu, Junqi Deng, Junyi Li, Tao Su, Dihu Chen and
Zixin Wang (Sun Yat-sen University)

Transaction-Accurate Interface Scheduling in High-Level Synthesis
John Sanguinetti, Michael Meredith and Sean Dart (Forte DS)

15:30  SESSION 4: MPSoCs

Multi-layer Configuration Exploration of MPSoCs for Streaming Applications
Deepak Mishrad, Rainer Doemer, Elaheh Bozorgzadeh, Yasaman Samei and Nga
Dang (University of California, Irvine)

Process Variation-aware Task Replication for Throughput Optimization in
Configurable MPSoCs
Love Singhal (Synopsys), Hessam Kooti and Eli Bozorgzadeh (University of
California, Irvine)

16:30  DEMO SESSION

Demonstrators Include:
National Instruments Lab at Berkeley
Cadence
Forte DS
COMPLEX Project


Social Event
We are pleased to invite the participants to a social dinner at
Buca di Beppo.
Buca di Beppo�is a collection of neighborhood restaurants with a lively
atmosphere and authentic Italian menu for all to enjoy. In the spirit of
Italian culture, the dishes are meant to be shared and served family-style,
perfect for passing around the table.

Dishes enjoyed for generations in villages throughout Italy inspire the
menu, giving Buca its authentic Italian fare. Buca continues to innovate and
create recipes beyond the traditional style by adding new menu items
inspired by Northern and Southern Italian cuisine.

Saturday, June 2
6:00 p.m.
855 Howard Street  San Francisco, CA 94103
The ESLsyn Social Dinner is included in the registration fee.

Description

The ever-increasing need for enhanced productivity in designing highly
complex electronic systems drives the evolution of design methods beyond the
traditional approaches. Virtual prototyping, design space exploration and
system synthesis with the goal of optimized and functionally correct product
implementations are needed for designing both HW and SW parts. ESL design
does not only provide system architects with the right tools to make the
right decisions about the system architecture, it includes the methodologies
and techniques that correlate the ESL model. A well-connected
ESL-to-implementation design flow is needed.

The system design teams expect newer and more efficient methods and tools
supporting better management of the design complexity and reduction of the
design cycle time all together, breaking the trend to compromise on the
evaluation of various design implementation options. Designing at higher
levels of abstraction is a viable way to better cope with the system design
complexity, to verify earlier in the design process and to increase code
reuse.

The Electronic System Level Synthesis Conference ESLsyn focuses on automated
system design methods that enable efficient modelling of systems to provide
the capability to synthesize HW platforms and embedded software with
particular aspects related to synthesis.

Co-located with DAC
The Design Automation Conference (DAC) is the premier event for the design
of electronic circuits and systems, and for EDA and silicon solutions. Now
in its 49th year, DAC features a wide array of technical presentations, as
well as more than 200 of the leading electronics design suppliers in a
colorful, well-attended trade show that, literally, attracts stakeholders
from around the world.
DAC is where the IC Design and EDA ecosystem learns, networks, and does
business. DAC is also where the latest technical research is presented. DAC
covers all topics related to the design complex systems on chip: Embedded
System design and verification down to physical layout verification & test.


Follow ESLsyn on LinkedIn!

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kedin.com/groups/ESLsyn-Electronic-System-Level-Synthesis-4197998>

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Resources last updated: 3/24/2016 6:35:54 PM