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Call for Papers -Deadline April 14 -Last Reminder! >Electronic System Level Synthesis Conference (ESLsyn) >San Diego, CA, June 5-6, 2011

[http://www.ecsi.org/sites/default/files/images/san%20diego2.png]
[http://www.ecsi.org/sites/default/files/images/ESLsyn-small.jpg]
Electronic System Level Synthesis Conference
June 5-6, 2011
San Diego, California, USA
Co-located with DAC!
Call for Contributions
Extended Submission Deadline - April 14!
Chair: Dan Gajski, University of California, Irvine
Co-Chair & Organization: Adam Morawiec, ECSI
Program Co-Chairs:
Philippe Coussy, Lab-STICC, Universit� de Bretagne Sud
Sandeep K. Shukla, Virginia Tech University

www.ecsi.org/eslsyn

ESLsyn is organized with the technical co-sponsorship of IEEE
and the IEEE Council on Electronic Design Automation (CEDA)
[http://www.ecsi.org/sites/default/files/images/CEDA_Logo_small2.jpg]
[http://www.ecsi.org/sites/default/files/images/IEEE.gif] In
In collaboration with Euromicro
 [http://www.ecsi.org/sites/default/files/images/Euromicro%20Logo_small3.png
]

Workshop Description
The ever increasing need for enhanced productivity in designing highly
complex electronic systems drives the evolution of design methods beyond the
traditional approaches. Virtual prototyping, design space exploration and
system synthesis with the goal of optimized and functionally correct product
implementation are needed for designing both HW and SW parts.
The system design teams expect newer and more efficient methods and tools
supporting better management of the design complexity and reduction of the
design cycle time all together, breaking the trend to compromise on the
evaluation of various design implementation options. Designing at higher
levels of abstraction is a viable way to better cope with the system design
complexity, to verify earlier in the design process and to increase code
reuse.
The Electronic System Level Synthesis Conference ESLsyn focuses on automated
system design methods that enable efficient modelling of systems to provide
the capability to synthesize HW platforms and embedded software with
particular aspects related to synthesis.

Target Audience

This conference will provide an overview of existing and emerging solutions
provided by both industrial partners (EDA companies) and research
institutions in the domain of ESL synthesis. It will give an outline of
synthesis methods and tools available currently in the market and discuss
their applicability, performance, strengths and user experiences. Finally,
the event will create a discussion platform for experience exchange between
providers of synthesis technology and industry users, but also will be a
forum to discuss scientific concepts and paradigms for the future evolution
of synthesis methods.

Topics
Cyber-Physical System/System/Platform: model-driven synthesis, models of
computation, virtual prototyping, design space exploration, design
methodologies, architectures, co-design, interface synthesis, partitioning,
performance analysis, optimization, modeling refinement, transformation,
generation, languages, formal specification and verification methods,
virtualization, target platforms: ASIC, FPGA, GPU, many- & multi-core, SOC
platforms, HW accelerators, ...
High-Level Synthesis, Behavioral Synthesis, Architectural Synthesis for HW
Design: hierarchical synthesis, algorithmic transformations, loop
transformations, scheduling & binding techniques, correctness, formal
verification, reliability, incremental synthesis, control-oriented
synthesis, low-power synthesis, performance-driven synthesis,
target-specific synthesis, multiple clock design, input languages & subsets,
internal representation, interaction with low-level synthesis,
certification, trade-off analysis, ...
Embedded Software Synthesis: programming models (including multi-core, GPU
programming models), correct-by-construction software synthesis,
intermediate representations, scheduling techniques, binding, communication
and synchronization protocols, middleware/hardware-dependent software,
performance analysis and optimization, domain-specific languages and methods
(AADL etc.), concurrent program synthesis, compilers for multi-/many- cores,
time triggered vs. event triggered models, synchronous programming models,
formal methods for embedded software design and verification, ...
The above list is not an exhaustive list of topics addressed by ESLsyn ;
contributions related to ESLsyn problems in general not listed here are
highly welcome. Submissions may be theoretical scientific papers, research
in progress, case studies, tool use cases and best practice, as well as
industry experiences.

Program Committee
Felice Balarin, Cadence Design Systems, USA
Shuvra Bhattacharyya, University of Maryland, USA
Thomas Bollaert, Mentor Graphics, France
Jens Brandt, University of Kaiserslautern, Germany
Forest Brewer, University of California, Santa Barbara, USA
Benjamin Carrion-Schafer, NEC Corporation, Japan
Jason Cong, University of California, Los Angeles, USA
Philippe Coussy, Lab-STICC, Universit� de Bretagne Sud, France
Steven Derrien, IRISA, France
Robert De Simone, INRIA, France
Mamoun Filali-Amine, IRIT, France
Daniel Gajski, University of California, Irvine, USA
Thierry Gautier, IRISA, France
Abdoulaye Gamati�, LIFL, France
Kim Gr�ttner, OFFIS, Germany
Yuko Hara-Azumi, Ritsumeikan University, Japan
Christian Haubelt, University of Erlangen-N�rnberg, Germany
Lech Jozwiak, TU Eindhoven, Netherland
Niraj K. Jha, Princeton University, USA
Ryan Kastner, University of California, San Diego, USA
Luciano Lavagno, Politecnico di Torino, Italy
Wayne Luk, Imperial College London, UK
Fr�d�ric Mallet, INRIA, France
Michael McNamara, Cadence Design Systems, USA
Michael Meredith, Forte Design Systems, USA
Maria Carmen Molina, Universidad Complutense de Madrid, Spain
Adam Morawiec, ECSI, France
Stephen Neuendorffer, Xilinx, USA
Bernhard Niemann, Fraunhofer, Germany
Rishiyur Nikhil, Bluespec, USA
Marc Pantel, IRIT, Universit� de Toulouse, France
Hiren Patel, University of Waterloo, Canada
Dumitru Potop-Butucaru , INRIA, France
Tanguy Risset, CITI - INSA Lyon, France
Eric Rutten, INRIA, France
John Sanguinetti, Forte Design Systems, USA
Sandeep Shukla, Virginia Tech University, USA
Johannes Stahl, Synopsys
Martin Strecker, IRIT, France
David Thomas, Imperial College London, UK
Hiroyuki Tomiyama, Ritsumeikan University, Japan
Eugenio Villar, University of Cantabria, Spain
Kazutoshi Wakabayashi, NEC Corporation, Japan
Hiroaki Yoshida, University of Tokyo, Japan

Submission Requirements
Authors should submit their full papers (up to 6 pages, double-column IEEE
format) in PDF through the web based submission system. Submitted papers
should be anonymous, are required to describe original unpublished work and
must not be under consideration for publication elsewhere.
ESLsyn will publish the proceedings including all accepted and presented
papers in the IEEExplore database of IEEE (pending agreement).
The conference proceedings will be also published in electronic form with
the ISBN and ISSN numbers and made available in the ECSI Resource Center.
Selected best papers will be published in a book by SPRINGER.
Full submission requirements, templates and submission page link can be
found at www.ecsi.org/eslsyn<http://www.ecsi.org/eslsyn>.

Important Dates

Extended Paper Submission Deadline:

Notification of Acceptance:

Camera Ready Papers:


April 1, 2011       April 14, 2011

April 28, 2011

May 16, 2011


Additional Information
Follow ESLsyn on LinkedIn!
[http://www.ecsi.org/sites/default/files/images/linkedin.jpg]<http://events.
linkedin.com/ESLsyn-Electronic-System-Level-Synthesis/pub/608563>
Call for 
Papers<http://www.ecsi.org/journal-electrical-and-computer-engineering>
Journal of Electrical and Computer Engineering
Special Issue on ESL Design Methodology
Deadline - July 1, 2011

Please, transfer this message to persons interested in this topic!
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Please click here<http://www.ecsi.org/remove-mailing-list> if you wish to be
removed from this mailing list.
Please do not respond to this email address. Direct contact information can
be found at www.ecsi.org<http://www.ecsi.org> .
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