I am experiencing an unexpected behavior with bus selectors: say you have a signal 'x' fed into a BusCreator. The resulting bus goes into a bus selector, which selects the 'x' signal. The selected signal goes into another bus selector, which then selects again the 'x' signal!
I would have expected the second bus not to recognize any signal, since its input is not a bus. Infacts, if the Bus Selector works on a 'x' signal not passing thorugh a Bus Creator, you'll get an error.
Why does this happen?
For instance, try this to see what I mean:
new_system('bus_trial_1')
add_block('built-in/Constant' ,'bus_trial_1/C1' ,'Position',[ 15 15 30 30])
add_block('built-in/BusCreator' ,'bus_trial_1/BC1','Position',[ 85 15 90 30],'Inputs','1')
add_block('built-in/BusSelector','bus_trial_1/BS1','Position',[155 15 160 30],'OutputSignals','x')
add_block('built-in/BusSelector','bus_trial_1/BS2','Position',[225 15 230 30],'OutputSignals','x')
add_block('built-in/BusSelector','bus_trial_1/BS3','Position',[295 15 300 30],'OutputSignals','x')
add_block('built-in/BusSelector','bus_trial_1/BS4','Position',[365 15 370 30],'OutputSignals','x')
add_block('built-in/Terminator' ,'bus_trial_1/T1' ,'Position',[435 15 450 30])
set_param(add_line('bus_trial_1','C1/1','BC1/1'),'Name','x')
add_line('bus_trial_1','BC1/1','BS1/1')
add_line('bus_trial_1','BS1/1','BS2/1')
add_line('bus_trial_1','BS2/1','BS3/1')
add_line('bus_trial_1','BS3/1','BS4/1')
add_line('bus_trial_1','BS4/1', 'T1/1')
open_system('bus_trial_1')
sim('bus_trial_1')
No errors are detected and all the Bus Selectors work selecting the 'x' signal, even if only the first one actually has a bus as an input....
new_system('bus_trial_2')
add_block('built-in/Constant' ,'bus_trial_2/C1' ,'Position',[ 15 15 30 30])
add_block('built-in/BusSelector','bus_trial_2/BS1','Position',[ 85 15 90 30],'OutputSignals','x')
add_block('built-in/Terminator' ,'bus_trial_2/T1' ,'Position',[155 15 170 30])
set_param(add_line('bus_trial_2','C1/1','BS1/1'),'Name','x')
add_line('bus_trial_2','BS1/1', 'T1/1')
open_system('bus_trial_2')
sim('bus_trial_2')
In this case the Bus Selector does not recognizes any signals within its input.
Is this behavior correct? Any drawback for it?
Thanks,
mytongka
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