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OS_ClaimProcessorVector on RO3.1

Can anyone remember a module that implemented OS_ClaimProcessorVector 
on RO3.1 - and what it was called? (SWI &69)

Thanks
-- 
Colin Ferris Cornwall UK
0
cferris
10/14/2016 8:19:30 AM
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On 14/10/2016 09:19, cferris@freeRemoveuk.com.invalid wrote:
> Can anyone remember a module that implemented OS_ClaimProcessorVector
> on RO3.1 - and what it was called? (SWI &69)

Don't remember that one. You aren't thinking of the OSCallASWI or 
OSClaimASWI modules?

---druck

0
druck
10/14/2016 6:39:17 PM
On 14/10/2016 19:39, druck wrote:
> On 14/10/2016 09:19, cferris@freeRemoveuk.com.invalid wrote:
>> Can anyone remember a module that implemented OS_ClaimProcessorVector
>> on RO3.1 - and what it was called? (SWI &69)
>
> Don't remember that one. You aren't thinking of the OSCallASWI or
> OSClaimASWI modules?

It's not in HAL26 either.

---druck

0
druck
10/14/2016 6:52:54 PM
On Friday, October 14, 2016 at 7:52:56 PM UTC+1, druck wrote:
> On 14/10/2016 19:39, druck wrote:
> > On 14/10/2016 09:19, cferris@freeRemoveuk.com.invalid wrote:
> >> Can anyone remember a module that implemented OS_ClaimProcessorVector
> >> on RO3.1 - and what it was called? (SWI &69)
> >
> > Don't remember that one. You aren't thinking of the OSCallASWI or
> > OSClaimASWI modules?
> 
> It's not in HAL26 either.
> 
> ---druck

Are you thinking of SYS "OS_CallAVector"? For a HAL-based machine
the command ed%=&A1<<16:SYS "OS_CallAVector",ed%,b%,256,,14,,,,42
will use the GraphicsV vector (42 - the answer to life) to read the
I2C location at &A1 (EDID data) (often not exposed to either
SYS "IIC_Control" or SYS "OS_IICOp").
0
svrsig
10/14/2016 8:59:41 PM
druck <news@druck.org.uk> wrote:
> On 14/10/2016 19:39, druck wrote:
> > On 14/10/2016 09:19, cferris@freeRemoveuk.com.invalid wrote:
> >> Can anyone remember a module that implemented OS_ClaimProcessorVector
> >> on RO3.1 - and what it was called? (SWI &69)
> >
> > Don't remember that one. You aren't thinking of the OSCallASWI or
> > OSClaimASWI modules?
> 
> It's not in HAL26 either.

I'm trying to understand how this might work.

The routine that you attach to the vector would be called in a different
mode on ARMv2 and ARMv3+ processors - SVC26/IRQ26 mode on ARMv2 (they didn't
have the 26 suffix then, of course), and Supervisor32, IRQ32, ABORT32, UND32,
etc on ARMv3 and later.

So it's not feasible to take code that would attach to a vector in
32 bit mode and move that to a 26 bit machine, because it will be expect to
be running in a mode the processor doesn't support.

It might be possible to go the other way - register a 26 bit handler on an
ARMv3 machine and drop into 26 bit mode - but that's no use on anything
later than a RiscPC.

Theo
0
Theo
10/14/2016 11:22:09 PM
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