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parallel processing #2

Further to some parallel processing comments here:
One of my Geos interfaces (maybe Topdesk), allows 2 programmes to be open
simultaneously, although they are not both processing at the same time;
useful for transferring data between open programmes.

When we use a printer set-up that has a buffer in the interface (Xetec, &
Xetec Gold), or printer (any modern inkjet), once the data reaches the
buffer we can continue another computer task.

I have a spooler that allows me to send text to be printed to mydisk
drive, then disconnect the drive from the computer, & continue to compute.

My C= disk manuals say that the 1541 has 2k, the 1571 4k, & the 1581 8k
usable ram. For the chaining suggestion.

I wondered about a parent programme that would run on one C= computer that
would send data to another C= computer via null modem cable, then proceed
to do one computing taskwhile the other C= computer operated on the
received data.
But I have never seen a programme that automatically accepted modem data &
proceeded to operate on it. 

It has been stated here before that the 128 cpu & the 64 cpu in a 128
cannot operate at the same time.  I suppose fast interrupts could give the
appearance of parallel work if fast switching were possible.

Does my cpm cartridge for my c64 replace the c64 cpu or co-operate with
it? I suspect the latter.

Just some random thoughts.  Anything practical?

John Elliott


0
ap721
1/19/2004 12:02:18 PM
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On Mon, 19 Jan 2004 ap721@chebucto.ns.ca.nospam wrote:

> Further to some parallel processing comments here:
> It has been stated here before that the 128 cpu & the 64 cpu in a 128
> cannot operate at the same time.  I suppose fast interrupts could give the
> appearance of parallel work if fast switching were possible.

There is no separate CPU for 64 mode in the 128.  Both modes are handled
by the 8502 processor.  You can switch control over to the Z80 (used for
booting the machine and for CP/M mode), but you cannot use both CPUs at
the same time.

> Does my cpm cartridge for my c64 replace the c64 cpu or co-operate with
> it? I suspect the latter.

The former.  It uses the DMA line on the expansion connector to disable
the 64's normal CPU and takes control of the address & data busses.  See
http://home.hccnet.nl/g.baltissen/c64_cpm.htm

- Dave
0
Dave
1/19/2004 1:30:31 PM
Dave Ross wrote:
<snip-and-tuck>
> 
> There is no separate CPU for 64 mode in the 128.  Both modes are handled
> by the 8502 processor.  You can switch control over to the Z80 (used for
> booting the machine and for CP/M mode), but you cannot use both CPUs at
> the same time.
> 

Hmmm, what about a hardware modification to allow both to run at the 
same time? I imagine there would be all sorts of timing conflicts with 
both processors accessing memory but I think it would still work as they 
both honor the bus busy lines.

*goes off to find the schematics*

Any thoughts?

0
Corin
1/19/2004 6:00:36 PM
"Corin Talkobt" <junk_mail@bellsouth.net> wrote in message
news:400C1B44.7060108@bellsouth.net...
> Dave Ross wrote:
> <snip-and-tuck>
> >
> > There is no separate CPU for 64 mode in the 128.  Both modes are handled
> > by the 8502 processor.  You can switch control over to the Z80 (used for
> > booting the machine and for CP/M mode), but you cannot use both CPUs at
> > the same time.
>
> Hmmm, what about a hardware modification to allow both to run at the
> same time? I imagine there would be all sorts of timing conflicts with
> both processors accessing memory but I think it would still work as they
> both honor the bus busy lines.

Unfortunately also the VIC wants to access the bus every now and then, so
that would make three processors running on the same bus. Also keep in mind
that the 8502 may require up to three cycles before it releases the bus. I
think the arbitration logic would become rather complex. I also believe the
8502 accesses the bus quite a lot, so running a Z80 in parallel would mean
slowing the 8502 down. It would be very impressive if someone manages to
pull this of, but I don't expect this to be an easy modification.

--
Peter van Merkerk
peter.van.merkerk(at)dse.nl



0
Peter
1/19/2004 7:08:49 PM
Peter van Merkerk wrote:

> 
> Unfortunately also the VIC wants to access the bus every now and then, so
> that would make three processors running on the same bus. Also keep in mind
> that the 8502 may require up to three cycles before it releases the bus. I
> think the arbitration logic would become rather complex. I also believe the
> 8502 accesses the bus quite a lot, so running a Z80 in parallel would mean
> slowing the 8502 down. It would be very impressive if someone manages to
> pull this of, but I don't expect this to be an easy modification.
> 

I think the arbitration logic is already set up on the C128 board - as 
both the 8502 and the Z80A have to contend with the VIC chip. All that 
would need to be done is to find some way to snip the wire that inhibits 
the other chip. That, and a reliable way of initializing both processors.

0
Corin
1/19/2004 8:46:44 PM
ap721@chebucto.ns.ca.nospam wrote:

> I wondered about a parent programme that would run on one C= computer that
> would send data to another C= computer via null modem cable, then proceed
> to do one computing taskwhile the other C= computer operated on the
> received data.
> But I have never seen a programme that automatically accepted modem data &
> proceeded to operate on it. 

The serial bus could be used as well. For connecting two C64 you don�t
even need special cables, and the software is not too difficult.
Disadvantage maybe is the speed, because of the serial transmission.
Without switching off the VIC, 700 bytes/second seems to be the
maximum.

Regards
Franz
0
kottira
1/19/2004 8:59:29 PM
"Corin Talkobt" <junk_mail@bellsouth.net> wrote in message
news:H1YOb.10419$%86.6713@bignews4.bellsouth.net...
> Peter van Merkerk wrote:
> >
> > Unfortunately also the VIC wants to access the bus every now and then,
so
> > that would make three processors running on the same bus. Also keep in
mind
> > that the 8502 may require up to three cycles before it releases the bus.
I
> > think the arbitration logic would become rather complex. I also believe
the
> > 8502 accesses the bus quite a lot, so running a Z80 in parallel would
mean
> > slowing the 8502 down. It would be very impressive if someone manages to
> > pull this of, but I don't expect this to be an easy modification.
>
> I think the arbitration logic is already set up on the C128 board - as
> both the 8502 and the Z80A have to contend with the VIC chip. All that
> would need to be done is to find some way to snip the wire that inhibits
> the other chip. That, and a reliable way of initializing both processors.

That is the easy part, just follow the /Z80EN line, and look at the /BUSACK
signal on the Z80 processor. Something else that is easy is to detect when
the Z80 wants to bus (/MEMREQ) and to halt the Z80 (/WAIT) when the 8502 is
using the bus. Unfortunately I see no way how to detect when the 8502 needs
the bus, but then again due to the nature of this processor that should be
nearly always. Probably the only way to run the Z80 and the 8502 in parallel
is to halt the 8502 when the Z80 wants to access memory (/MEMREQ), wait
three cycles (keeping the /WAIT line on the Z80 low), then let the Z80 take
over the bus, wait for the Z80 to complete its bus cycle than give the bus
back to the 8502. Unfortunately this procedure would slowdown both the 8502
and the Z80 quite a bit.

There are no doubt a couple of other details I forgot. But I think that if
running a 8502 and a Z80 in parallel is easy and would be a matter of just
snipping a wire, the commodore engineers would have done so.

--
Peter van Merkerk
peter.van.merkerk(at)dse.nl


0
Peter
1/19/2004 11:00:20 PM
Peter van Merkerk wrote:
> "Corin Talkobt" <junk_mail@bellsouth.net> wrote in message
> news:H1YOb.10419$%86.6713@bignews4.bellsouth.net...
> 
>>Peter van Merkerk wrote:
>>
>>>Unfortunately also the VIC wants to access the bus every now and then,
> 
> so
> 
>>>that would make three processors running on the same bus. Also keep in
> 
> mind
> 
>>>that the 8502 may require up to three cycles before it releases the bus.
> 
> I
> 
>>>think the arbitration logic would become rather complex. I also believe
> 
> the
> 
>>>8502 accesses the bus quite a lot, so running a Z80 in parallel would
> 
> mean
> 
>>>slowing the 8502 down. It would be very impressive if someone manages to
>>>pull this of, but I don't expect this to be an easy modification.
>>
>>I think the arbitration logic is already set up on the C128 board - as
>>both the 8502 and the Z80A have to contend with the VIC chip. All that
>>would need to be done is to find some way to snip the wire that inhibits
>>the other chip. That, and a reliable way of initializing both processors.
> 
> 
> That is the easy part, just follow the /Z80EN line, and look at the /BUSACK
> signal on the Z80 processor. Something else that is easy is to detect when
> the Z80 wants to bus (/MEMREQ) and to halt the Z80 (/WAIT) when the 8502 is
> using the bus. Unfortunately I see no way how to detect when the 8502 needs
> the bus, but then again due to the nature of this processor that should be
> nearly always. Probably the only way to run the Z80 and the 8502 in parallel
> is to halt the 8502 when the Z80 wants to access memory (/MEMREQ), wait
> three cycles (keeping the /WAIT line on the Z80 low), then let the Z80 take
> over the bus, wait for the Z80 to complete its bus cycle than give the bus
> back to the 8502. Unfortunately this procedure would slowdown both the 8502
> and the Z80 quite a bit.
> 
> There are no doubt a couple of other details I forgot. But I think that if
> running a 8502 and a Z80 in parallel is easy and would be a matter of just
> snipping a wire, the commodore engineers would have done so.
> 
> --
> Peter van Merkerk
> peter.van.merkerk(at)dse.nl

Yes, the 8502 and Z80 would have to share access - however the VIC chip 
inhibits the 8502 and hence the Z80 is / could be wired the same way. 
It's been ages since I looked into the timings of things but, other than 
a hack, I imagine the sharing between the 2 processers and the VIC chip 
would be _very_ slow.

Actually, the C= engineers would have been crazy to have both the 8502 
and Z80 running at the same time - it would have ruined C=64 
compatibility, Z80 CP/M mode etc - and made a big chore for programmers.

As for the bus, just assume the 8502 always has access - when the Z80 
needs it, have it raise the RDY line to inhibit the 8502. Once the AEC 
line goes high, then the Z80 can resume.

Heh, now that it's mostly figured out I'm half tempted to take my 
wire-wrap stuff and get started - just gotta figure out how to get the 
memory initialized properly.

0
Corin
1/20/2004 1:10:45 AM
 
 'Lo John:

Group: comp.sys.cbm Date: Mon, Jan 19, 2004, 12:02pm (CST+6) From:
ap721@chebucto.ns.ca.nospam 

script:

>Does my cpm cartridge for my c64 
>replace the c64 cpu or co-operate 
>with it? I suspect the latter. 

Correct.  The C=3D CP/M manual says that the 6510 is used for I/O.
However, they do not run at the same time.

When the Z80 needs I/O it puts the data in a certain place that the 6510
knows to look for it,=85 and sets a bit which both turns on the 6510 and
turns off the Z80.

When the 6510 is finished with the I/O, it puts the data where the Z80
will look for it,=85 and resets the bit so that the 6510 is turned off
and the Z80 is turned on.

HTH.

Actually, parallel processing of 8-bits sounds=85 "cutely" interesting.
Not much use, (except to learn how to "Beowulf",=85 ) but interesting.

salaam,
dowcom

-- 
  To e-mail me, add the character zero to "dowcom".  i.e.:
dowcom(zero)(at)webtv(dot)net.

http://community.webtv.net/dowcom/DOWCOMSAMSTRADGUIDE

MSWindows is television,=85 Linux is radar.

0
dowcom
1/20/2004 7:25:37 AM
<snip>
> Yes, the 8502 and Z80 would have to share access - however the VIC chip
> inhibits the 8502 and hence the Z80 is / could be wired the same way.
> It's been ages since I looked into the timings of things but, other than
> a hack, I imagine the sharing between the 2 processers and the VIC chip
> would be _very_ slow.
>
> Actually, the C= engineers would have been crazy to have both the 8502
> and Z80 running at the same time - it would have ruined C=64
> compatibility, Z80 CP/M mode etc - and made a big chore for programmers.
>
> As for the bus, just assume the 8502 always has access - when the Z80
> needs it, have it raise the RDY line to inhibit the 8502. Once the AEC
> line goes high, then the Z80 can resume.

That was basically the idea I was having. I don't know how often the Z80
wants to access the bus; I expect it to be a lot less than a 8502 since a
Z80 needs a lot more clocks per instruction and a clock cycle on Z80 is not
the same as a machine cycle.

> Heh, now that it's mostly figured out I'm half tempted to take my
> wire-wrap stuff and get started - just gotta figure out how to get the
> memory initialized properly.

If you do so I'd really like hearing about it. I remember that 15 years ago
I digged thought the C128 programmer reference manual (which also discusses
the C128's hardware) to see if the Z80 could run in parallel. At that time
I didn't really have the expertise to fully understand workings of the
various busses, so there the story ended.

--
Peter van Merkerk
peter.van.merkerk(at)dse.nl



0
Peter
1/20/2004 10:33:34 AM
<ap721@chebucto.ns.ca.nospam> wrote in message news:bugh0a$104$1@News.Dal.Ca...
> I wondered about a parent programme that would run on one C= computer that
> would send data to another C= computer via null modem cable, then proceed
> to do one computing taskwhile the other C= computer operated on the
> received data.
> But I have never seen a programme that automatically accepted modem data &
> proceeded to operate on it.
>
>

There was a PAL demo not so long ago, dual head like that used some cable to
connect 2 C64's and run the demo code in sync.


0
Nathan
1/20/2004 11:34:57 AM
Reply: