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Freescale COP/Jtag how does it work?

Hi,

anyone have documentation on how the Freescale COP/Jtag works?

I could not find anything on the Freescale website. I can find
all the information on 8xx/BDM but they aren't releasing any info
on COP. The CPU that I am interested in is the mpc8272.
0
b
12/11/2005 8:06:42 PM
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about 5 years ago, when the 8240 was still subject
to NDA, I asked about the JTAG details.
I did get the BSDL file (which is what I was after),
but although I had signed an NDA the guy providing
the info told me he was not authorized to give me
the information on the JTAG insides...
Apparently they have gone the wrong path by
wanting not only to sell the chips but also collect
the change for tooling - or are instructed to do
so from "above" in order to maintain control, or,
most likely, both.
Fortunately, the PPC architecture is clear enough
and one can do without the additional facilities
they may have.

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

0
Dimiter
12/11/2005 9:32:15 PM
When I asked for COP details a few years ago, Motorola told me they
couldn't give out that information because it was proprietary to IBM.

  -=- Andrew Klossner
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andrew
12/12/2005 4:37:40 PM
This could well be the case, of course.
On the other hand, I see some non-IBM tool manufacturers
who appear to have received the data - but I have not dug
deep enough into that (no such interest - at least for now).

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

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Dimiter
12/12/2005 4:47:48 PM
Freescales JTAG interface is not proprietary. It is the industry IEEE 1149.1
standard. Anyone can use the JTAG interface to do boundary interconnect
test, and the BSDL file is publicly available.

The Debug Port (COP), on the other hand, is proprietary. They only share
this proprietary debug port information with their 3rd party tool vendors.
Customers can contact these 3rd party tool vendors, or Freescale's own
DevTech (formerly Metrowerks) to provide solutions such as  JTAG emulators.

"b. ma" <bma377@comcast.net> wrote in message
news:C_qdnTAke-TLGwHenZ2dnUVZ_tudnZ2d@comcast.com...
> Hi,
>
> anyone have documentation on how the Freescale COP/Jtag works?
>
> I could not find anything on the Freescale website. I can find
> all the information on 8xx/BDM but they aren't releasing any info
> on COP. The CPU that I am interested in is the mpc8272.


0
Malcolm
12/13/2005 5:01:54 PM
So it is as bad as I suspected.
I manage it without their tools and without the
debug port, and I am not sure I'll ever use it, but
this path is clearly customer unfriendly.
I have about 20 megabytes of sources written for
68k and PPC platforms, a full-blown OS (superior
to what their third-party tool vendors could ever dream
of), but I am not entitled to the data...

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

0
Dimiter
12/13/2005 8:14:00 PM
I was thinking of writing a COP-aware GDB patch. But it looks like
I am out of luck. Phooey ;-(


Malcolm Ward wrote:
> Freescales JTAG interface is not proprietary. It is the industry IEEE 1149.1
> standard. Anyone can use the JTAG interface to do boundary interconnect
> test, and the BSDL file is publicly available.
> 
> The Debug Port (COP), on the other hand, is proprietary. They only share
> this proprietary debug port information with their 3rd party tool vendors.
> Customers can contact these 3rd party tool vendors, or Freescale's own
> DevTech (formerly Metrowerks) to provide solutions such as  JTAG emulators.
> 
> "b. ma" <bma377@comcast.net> wrote in message
> news:C_qdnTAke-TLGwHenZ2dnUVZ_tudnZ2d@comcast.com...
> 
>>Hi,
>>
>>anyone have documentation on how the Freescale COP/Jtag works?
>>
>>I could not find anything on the Freescale website. I can find
>>all the information on 8xx/BDM but they aren't releasing any info
>>on COP. The CPU that I am interested in is the mpc8272.
> 
> 
> 
0
b
12/13/2005 8:25:35 PM
Malcolm Ward <ra7958@freescale.com> wrote:
: 
: Freescales JTAG interface is not proprietary. It is the industry IEEE 1149.1
: standard. Anyone can use the JTAG interface to do boundary interconnect
: test, and the BSDL file is publicly available.

If I'm not totally mistaken, there are two sides of that story.
Or rather, there are two JTAG chains - one for reading back the logic state
of each of the external pins (which is the original intention of the JTAG
_boundary_ scan system.) This is documented by means of BSDL files. This
chain is, of course, utterly useless. 

But there is also another alternative JTAG chain which reads/writes all the
CPU core and peripheral control/data registers. This chain is undocumented.
This is the chain we want. At least this is how it is done in AVRs.

And none of the manufacturers are the slightest insterested in documenting
this interface in order to attract third parties tool vendors by forcing
customers to by their tools just to access the built in debug circuitry.
In other words - a deal you just can't say no to. They'll even throw in a
horse' head in the deal for you. 

I just wish a sufficent number of large volume customers would slap them on
their fingers for this practise. But no, these companies get 'free' support
from IBM/Freescale/ARM/Philips/whatever. 

-- 
  ******************************************************
  Never ever underestimate the power of human stupidity.
  -Robert Anson Heinlein

		GeirFRS@INVALID.and.so.forth
  ******************************************************
0
Geir
12/15/2005 11:14:12 PM
On Thu, 15 Dec 2005, Geir Frode Raanes S�rensen wrote:

> Malcolm Ward <ra7958@freescale.com> wrote:
> : 
> : Freescales JTAG interface is not proprietary. It is the industry IEEE 1149.1
> : standard. Anyone can use the JTAG interface to do boundary interconnect
> : test, and the BSDL file is publicly available.
> 
> If I'm not totally mistaken, there are two sides of that story.
> Or rather, there are two JTAG chains - one for reading back the logic state
> of each of the external pins (which is the original intention of the JTAG
> _boundary_ scan system.) This is documented by means of BSDL files. This
> chain is, of course, utterly useless. 
> 
> But there is also another alternative JTAG chain which reads/writes all the
> CPU core and peripheral control/data registers. This chain is undocumented.
> This is the chain we want. At least this is how it is done in AVRs.

How hard would it be to just put some probes on the lines and watch what 
the proprietary software is doing?  It can't be that bad to figure out 
if you really wanted to...

If they document it, it means that they have to update that for every 
rev and have to support it for every rev.  I can understand why they 
wouldn't want to do that, the per-rev documentation for regular chip 
functionality is crappy enough as-is.

TG
0
Terry
12/16/2005 3:13:24 AM
> How hard would it be to just put some probes on the lines and watch what
> the proprietary software is doing?  It can't be that bad to figure out
> if you really wanted to...

It will probably not be very hard - a week or two work.
After you have paid them for their tool....

> If they document it, it means that they have to update that for every
> rev and have to support it for every rev.  I can understand why they
> wouldn't want to do that, the per-rev documentation for regular chip
> functionality is crappy enough as-is.

I am really tired of such nonsence spread by people
who either do not understand the issue or have an
interest to have the data stay secret (I have heard
more than enough of it on a similar issue regarding
another, non-CPU product of another manufacturer).
 The chip makers always have the data in a publishable
form, this is how they spread it among the selected
circle of "third party manufacturers". The thing
is, they keep it secret in order to maintain
control over the development capabilities
of those who use their products - as much
as they can do so. Clearly a hositle policy.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

0
Dimiter
12/16/2005 10:57:14 AM
"Dimiter Popoff <dp@tgi-sci.com>" <dp@tgi-sci.com> wrote:
:> How hard would it be to just put some probes on the lines and watch what
:> the proprietary software is doing?  It can't be that bad to figure out
:> if you really wanted to...
: 
: It will probably not be very hard - a week or two work.
: After you have paid them for their tool....

Again, in the case of Atmel AVRs, the tools are not that horrendously
expensive ($200) to buy. Probably since they're up against Microchip wich
is highly entrenched in the hobbyist market. And people - including me -
buy them. It has been a year or two with dedicated JTAG logger projects and
still no eureka. Progress yes, but no breaktrough.
 
: I am really tired of such nonsence spread by people
: who either do not understand the issue or have an
: interest to have the data stay secret

Ditto.

-- 
  ******************************************************
  Never ever underestimate the power of human stupidity.
  -Robert Anson Heinlein

		GeirFRS@INVALID.and.so.forth
  ******************************************************
0
Geir
12/16/2005 10:22:31 PM
<dp@tgi-sci.com> wrote in message 
news:1134730634.885879.190790@o13g2000cwo.googlegroups.com...
>> How hard would it be to just put some probes on the lines and watch what
>> the proprietary software is doing?  It can't be that bad to figure out
>> if you really wanted to...
>
> It will probably not be very hard - a week or two work.
> After you have paid them for their tool....

  Do you even know how COP works?  It isn't a secret command
port.  It is very low level control of every scannable latch on the chip.
There are over 32k latches on some subchains.  This is why whenever
the processor is revised, so do the COP definition.  While you can easily
read every state, you can also easily break everything.

 So, good luck with that one-week decoding project.

>> If they document it, it means that they have to update that for every
>> rev and have to support it for every rev.  I can understand why they
>> wouldn't want to do that, the per-rev documentation for regular chip
>> functionality is crappy enough as-is.
>
> I am really tired of such nonsence spread by people
> who either do not understand the issue or have an
> interest to have the data stay secret (I have heard
> more than enough of it on a similar issue regarding
> another, non-CPU product of another manufacturer).
> The chip makers always have the data in a publishable
> form, this is how they spread it among the selected
> circle of "third party manufacturers". The thing
> is, they keep it secret in order to maintain
> control over the development capabilities
> of those who use their products - as much
> as they can do so. Clearly a hositle policy.

  Wow, you seem kind of hostile.   They "always" have the data
in "publishable" form, you say?

  The simplest answer is in fact the correct one: it's a big support hassle, 
as
the support mechanism is not a printed book, but a database extracted from
the chip design database and a lot of macros.

  Freescale only supports COP through a tier of tool vendors to minimize the
load on the one guy who does all this (hi "D.").  The ROI of opening it up 
to
everyone just isn't there.

Gary M.


0
Gary
12/17/2005 5:09:57 AM
> 
> 
>   Wow, you seem kind of hostile.   They "always" have the data
> in "publishable" form, you say?
> 
>   The simplest answer is in fact the correct one: it's a big support hassle, 
> as
> the support mechanism is not a printed book, but a database extracted from
> the chip design database and a lot of macros.
> 
>   Freescale only supports COP through a tier of tool vendors to minimize the
> load on the one guy who does all this (hi "D.").  The ROI of opening it up 
> to
> everyone just isn't there.
> 
> Gary M.

I just don't see how they could let the tool vendors know without the 
information in some "publishable" form. So I don't buy your argument.

The cheapest way for me to reverse engineer this thing is to buy a 
macraiger wiggler ($150) and put a logic analyzer on it while running
OCD Commander. It may be a 1 week job or 6 months. I don't know. I may
lose interest and work on something more interesting. This is a hobby 
for me, so I may not want to spend the $150. There are plenty of other
open source projects that need help.
0
bma
12/17/2005 6:23:54 AM
>> How hard would it be to just put some probes on the lines and watch what
>> the proprietary software is doing?  It can't be that bad to figure out
>> if you really wanted to...
>
> It will probably not be very hard - a week or two work.
> After you have paid them for their tool....
>
> Do you even know how COP works?

Hm, did you read my postings above? I do know how
the BDM works, which was published. Except for being accessed
via JTAG rather than the  BDM port - and the chip specific
diferences, which are most of the secret we are talking about,
it should be the same.

For further information on what I know have a look at
my companies website, pretty indicative. I have done
the designs, I have written the OS under which everything
is runing, I have written the JTAG tools, I have written
the compilers/assemblers/linkers which are used, and I
have written the debug tools which run without using the
COP interface - and everything else I cannot think of now.


Do you even know how the COP works, Gary M.?



>  Wow, you seem kind of hostile.

No. Just tired of nonsense spread by people who do not
understand the issue or have an interest
the data to stay secret. ...(Hopefully I typed it clearly enough
this time).

>  They "always" have the data in "publishable" form, you say?
>
>The simplest answer is in fact the correct one: it's a big support hassle,
> as
> the support mechanism is not a printed book, but a database extracted from
> the chip design database and a lot of macros.

So you do understand that they do have the information
in a publishable form.
Just put it across, it does not need to be any different from
what it is when given the selected circle it is given anyway.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

0
Dimiter
12/17/2005 12:56:32 PM
On Sat, 17 Dec 2005, Dimiter Popoff wrote:

> >> How hard would it be to just put some probes on the lines and watch what
> >> the proprietary software is doing?  It can't be that bad to figure out
> >> if you really wanted to...
> >
> > It will probably not be very hard - a week or two work.
> > After you have paid them for their tool....
> >
> > Do you even know how COP works?

[snip]

> Do you even know how the COP works, Gary M.?

You do know who Gary M. is, right?

TG
0
Terry
12/17/2005 1:33:37 PM
Reply: