Problem getting HDLC tx interrupt

Hi people,
I've been trying to do a simple loopback test using HDLC/SCC. Here is
my initialization sequence:
1) Set parallel io pins 30-31 for internal loopback
 pdird: 0x2
 ppard: 0x3
 psord: 0x2
2) set rx/tx clocks for scc1 using brg3
  brgc3: 0x000100A8
  cmxscr: 0x12000000
3) Issue a stop_tx command to the cpm
4) Configure dsr & psmr
 dsr: 0x7e7e
 psmr: 0x2800
5) Configure hdlc pram
6) Initialize rx/tx bds(all located in dpram).
7) Establish bd rbase/tbase
8) Initialize sccm register & clear scc events
9) Enable interrupts to scc1 through simr_l register
10) Issue CPM init/restart
11) Enable rx/tx transmission through gsmr_l
12) Finally, i point the bd's buffer pointer to a test string and set
the R bit for that bd.

I've failed in obtaining any transmission related interrupt using this
process. I suspect something related to clock configuration, though
couldn't resolve the issue.
Any one can point out where I am doing wrong?


yamanc (1)
2/8/2008 1:52:27 PM
comp.sys.powerpc.tech 819 articles. 1 followers. Post Follow

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Using MPC8260, sorry about the second post.
2/8/2008 1:55:31 PM