powerpc sync and eieio instructions
I have some problems with PowerPC syncronization instructions. In
particular I would know when sync and eieio instructions must be used.
I have the source code of a real time operating system for a single
processor board (MVME6100 with MPC7457) and I have notice the use of
sync, isync and eieio instructions. The question is: the
syncronization instruction should be used only in a multiprocessor
context, or not?
I have read the Reference Manual and the Programming Environments
guide but I'm confused.
Can someone explain to me why sync and eieio should be used or suggest
me a link?
...sync vs. eieio on powerpc
Got a mac I'm playing around with now. Mostly inline assembler.
eieio seems to order the memory accesses whereas sync actually
waits for accesses to complete to storage before permitting
subsequent accesses. So eieio seems adequate for most stuff but
all the examples use sync for release semantics. I'm not sure
why since eieio will work also.
And I have no clue why the examples use isync for acquire semantics.
It will work but so will eieio.
Timings on a 1.2 ghz G4 show... well now it shows isync as quicker
than eieio. Have to work on that timing program. I'm gett...PowerPC sync vs eieio.
We have a BSP from AcroMag for a PMC I/O board. The "vxWorks drivers"
simply swap data from Big Endian to PCI Little Endian. I examine the
D/A registers manually from the shell. The conversions worked well.
When I tried to do the conversions via software, they failed. I saw
many glitches on an osilliscope. I instrumented the code with
WindView and reduced my conversion times to the documented 13 uS.
However, in order to get multiple channels to work I needed to use a
sequence of "eieio" followed by "sync". The way the AcroMag D/A works
is to write a single...Can eieio PowerPC instruction be used on MPC5566?
We have been using PowerPC eieio(Enforce-In-Order Execution of I/O
assembly language instruction on Freescale MPC500 Famil
Can we use this instruction on Freescale MPC5500 Family Microcontrollers
for example MPC5566? If yes, do we need to modify any registers to mak
this instruction work?
> We have been using PowerPC eieio(Enforce-In-Order Execution of I/O)
> assembly language instruction on Freescale MPC500 Family
> Can we use this instruction on Freescale MPC5500 Family Microcontrollers,
> ...Lead Sys Tech and Sys Admin Web Services
I work on Cox Communications' internal hiring team at our headquarters
in Atlanta (Fortune 500 company, 6.3 million subscribers nationwide).
I have a couple positions here in Atlanta that require Solaris
expertise and just wanted to see if any members of this group might be
interested or know someone that may be. Please forgive me if this is
not an appropriate use of the board--I read through the Style Guide
and it appears that this is appropriate. Please feel free to reach me
directly at firstname.lastname@example.org.
The first position, System Administrator Web Services, requires a UNIX
...sync.rb difference between Sync::UN, Sync::EX and Sync::SH
In sync.rb what are Sync::UN, Sync::EX and Sync::SH all about?
Oh, one other thing. SyncEnumerator has nothing to do with Sync right?
Maybe it would be better if were named something else (TandemEnumerator
come to mind).
No one know? I assume Sync::EX when underlying data is gogin to change
and Sync::SH when it's not? Can EX just be used alwasy instead?
...PowerPC eieio instuction
I want to write one VME address followed by a read of a second address. This
is done on a PowerPC 2306. The write must complete on the VME device before
the read is performed. Is it sufficient to use the 'eieio' instruction
*(0x0020) = 4;
char byte = *(0x0024);
Chris, the Motorola 2306 board has an MPC604 PowerPC, therefore, the
use of the 'eieio' instruction is highly recommended. But, you need
to do one more step to ensure that your write is completed before the
read: use the...What are files Z80.SYS, Z80CCP.SYS and PRMTVPVT.SYS for?
Had a good Christmas this weekend?
I came across diskettes with "Mailmerge 3.0 and Calcstar version 1.45 for CP/M
8080", that seem to be for a Dec Rainbow machine.
Besides a Mailmerge overlay and the Calcstar files, some CP/M and some CP/M-86
files, there are three files on the diskettes that I never have heard of before:
Z80.SYS, Z80CCP.SYS and PRMTVPVT.SYS.
There are no ASCII texts in PRMTVPVT.SYS.
The only ASCII text in Z80.SYS (at the end of the file) is "EI SPHLDI
XCHGPCHLXTHLRET HLT CMC STC CMA DAA RAR RAL RRC RLC NOP CPI ORI XRI ANI SBI IN
SUI OUT ACI ADI CALLJMP LDA...where are the PowerPC 970 tech docs?
I apparently am not smart enough to find a single actual hardware
reference document on the PowerPC 970. Just a list of all the
instruction latencies will do.
I don't want to believe that such a document isn't publicly
available, yet I've looked high and low and haven't seen it.
Can someone point me in the right direction?
In article <email@example.com>,
firstname.lastname@example.org (Jason Papadopoulos) wrote:
> I apparently am not smart enough to find a single actual hardware
> reference document on the PowerPC 970. Just a list of...PowerPC 7455 eieio and gcc
I'm developing a device driver for a PowerPC 7455, and am having
problems with out of order accesses reaching the device. I'm using GCC
2.96 to build the driver, and if I
manually inline "eieio" instructions after the write accesses, the
ordering is correct. My question is, shouldn't these instructions be
automatically inserted by the compiler if the pointer I'm accessing is
declared as volatile? Is there some a compiler switch I should be
using? The same driver works perfectly on a 7410 board, without the
inserted eieio instructions. Right no...Powerpc I/O memory, linux, mmap and eieio
This week I inherited a buggy linux 2.4 device driver which controls a
device through I/O memory. Most of the known bugs were caused by direct
pointer dereferencing to the I/O memory space, without proper use of
readb()/writeb() and friends, so those were easy to fix.
The next step would be to move a big part of the code to userspace,
because a lot of the driver consists of 3d party code which does only do
memory I/O and thus should not necessarily have to live in the kernel.
Accessing the I/O memory should be using mmap() from userspace, but how
should I properly access this memory...When is the "sync" instruction required for the PPC750
Is anybody other there how could help me with this. I am look for a
simple explanation about the usage of the sync instruction. A table,
which specifies whether "sync" is necessary or not for a specific asm
instruction would also help. Unfortunatelly the IBM user's manual does
not help a lot.
Thanks a lot,
> Is anybody other there how could help me with this. I am look for a
> simple explanation about the usage of the sync instruction. A table,
> which specifies whether "sync" is necessary or not for a specific asm
> instruction wou...Powerpc I/O memory, linux, mmap and eieio
I bet this is not what you want:
0: 3c1c0000 lui gp,0x0
4: 279c0000 addiu gp,gp,0
8: 0399e021 addu gp,gp,t9
c: 00057080 sll t6,a1,0x2
10: 0004c880 sll t9,a0,0x2
14: 8f8f0000 lw t7,0(gp)
18: 00000000 nop
1c: 032f6021 addu t4,t9,t7
20: 01cf6821 addu t5,t6,t7
24: 8d820000 lw v0,0(t4)
28: 8da90000 lw t1,0(t5)
2c: 8f980000 lw t8,0(gp)
30: 01223823 subu a3,t1,v0
34: 00e70018 mult a3,a3
38: 03385021 addu t2,t9,t8
3c: 01d85821 addu t3,t6,t8
40: 8d680000 lw t0,0(t3)
44: 8d430000 lw v1,0(t2)
48: 00000000 nop
4c: ...How to get file descriptors of sys.stdin, sys.stdout and sys.stderr?
How to get file descriptors of sys.stdin, sys.stdout and sys.stderr?
On 11/13/2014 7:51 PM, email@example.com wrote:
in 4 different threads
> How to get file descriptors of sys.stdin, sys.stdout and sys.stderr?
> fileno() in not supported. Is it only in 3.1? What is the workaround?
> io.UnsupportedOperation: fileno
> How to give a file descriptor number to this function? How to get a
file descriptor number?
Satish, you are acting like the variety of troll called a Help Vampire.
One of the symptoms is hogging the newsgroup by starting multiple
threads a da...