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sync and eieio instruction

Hi all.
I have some problems with PowerPC syncronization instructions. In
particular I would know when sync and eieio instructions must be used.
I have the source code of a real time operating system for a single
processor board (MVME6100 with MPC7457) and I have notice the use of
sync, isync and eieio instructions. The question is: the
syncronization instruction should be used only in a multiprocessor
context, or not?
I have read the Reference Manual and the Programming Environments
guide but I'm confused.
Can someone explain to me why sync and eieio should be used or suggest
me a link?

Thanks!
0
lc.flno (3)
4/18/2008 7:19:23 AM
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lc.flno@gmail.com wrote:
> Can someone explain to me why sync and eieio should be used or suggest
> me a link?

For a short explanation, see "Memory-mapped I/O" at
http://www.go-ecs.com/ppc/ppctek1.htm


For the full reference, download the ISA (Instruction Set Architecture) 
documentation from 
http://www.power.org/resources/reading/PowerISA_V2.05.pdf, then read 
chapter 1.7.1 "Storage Access Ordering" (p.413ff) and chapter 3.4.3 
"Memory Barrier Instructions" (p.446-449).

0
Hagen
4/18/2008 1:58:10 PM
In article 
<07442557-9e34-4356-ae02-7d059da5f7c9@x41g2000hsb.googlegroups.com>,
 lc.flno@gmail.com wrote:

> I have some problems with PowerPC syncronization instructions. In
> particular I would know when sync and eieio instructions must be used.
> I have the source code of a real time operating system for a single
> processor board (MVME6100 with MPC7457) and I have notice the use of
> sync, isync and eieio instructions. The question is: the
> syncronization instruction should be used only in a multiprocessor
> context, or not?

No. You definitely also need them in case of memory mapped I/O (hence 
the name eieio). The reason is that without these instructions, the cpu 
is free to reorder reads/writes and perform load/store combining if it 
does not detect any dependencies. eieio only order writes (and prevents 
load/store combining), sync orders both reads and writes.

Note that eieio only orders writes to the same class of memory (the two 
classes are explained in the documentation). I.e. a write to class 1 and 
a write to class 2 won't be ordered relative to each other, but two 
writes to class 1 (or two to class 2) will be ordered.

sync orders everything.

isync orders instruction execution, mostly used to prevent the (out of 
ordeer) execution of code inside a critical section before the lock 
protecting it has actually been acquired.

An extensive discussion can be found here: 
http://www-128.ibm.com/developerworks/eserver/articles/powerpc.html

Also keep in mind that some ppc's have errata requiring extra isync's 
here and there, so check the user manual of your MPC7457 for potential 
pitfalls). 


Jonas
0
Jonas
4/18/2008 2:35:45 PM
Here's a link to an appnote on using Sync instructions on PowerPC

http://www.freescale.com/files/32bit/doc/app_note/AN3441.pdf?fsrch=1

 ... Paul


On Apr 18, 10:35 am, Jonas Maebe
<Jonas.Ma...@rug.SPAM.ac.ME.be.NOT.invalid> wrote:
> In article
> <07442557-9e34-4356-ae02-7d059da5f...@x41g2000hsb.googlegroups.com>,
>
>  lc.f...@gmail.com wrote:
> > I have some problems with PowerPC syncronization instructions. In
> > particular I would know when sync and eieio instructions must be used.
> > I have the source code of a real time operating system for a single
> > processor board (MVME6100 with MPC7457) and I have notice the use of
> > sync, isync and eieio instructions. The question is: the
> > syncronization instruction should be used only in a multiprocessor
> > context, or not?
>
> No. You definitely also need them in case of memory mapped I/O (hence
> the name eieio). The reason is that without these instructions, the cpu
> is free to reorder reads/writes and perform load/store combining if it
> does not detect any dependencies. eieio only order writes (and prevents
> load/store combining), sync orders both reads and writes.
>
> Note that eieio only orders writes to the same class of memory (the two
> classes are explained in the documentation). I.e. a write to class 1 and
> a write to class 2 won't be ordered relative to each other, but two
> writes to class 1 (or two to class 2) will be ordered.
>
> sync orders everything.
>
> isync orders instruction execution, mostly used to prevent the (out of
> ordeer) execution of code inside a critical section before the lock
> protecting it has actually been acquired.
>
> An extensive discussion can be found here:http://www-128.ibm.com/developerworks/eserver/articles/powerpc.html
>
> Also keep in mind that some ppc's have errata requiring extra isync's
> here and there, so check the user manual of your MPC7457 for potential
> pitfalls).
>
> Jonas

\\
0
Paul
4/22/2008 12:44:59 PM
Hi, I've read yours proposed references but I've still some doubts.

The code that confused me is that (about MMU initialization):

Page Table Updates (from MPC7450UM -> 5.5.3)

Thus the following code should be used:
/* Code for Modifying a Page Table Entry */
/* First delete the current page table entry */
PTEV <- 0/* (other fields don=92t matter) */
sync /* ensure update completed */
tlbie(old_EA) /* invalidate old translation */
eieio /* order tlbie before tlbsync */
tlbsync /* ensure tlbie completed on all processors */
sync /* ensure tlbsync completed */
/* Then add new PTE over old */
PTERPN,R,C,WIMG,PP <- new values
eieio /* order 1st PTE update before 2nd */
PTEVSID,API,H,V <- new values (V=3D1)
sync /* ensure updates completed */

And also this explanation:
(from MPC7450UM -> 3.3.3.5 Enforcing Store Ordering with Respect to
Loads)

The PowerPC architecture specifies that an eieio instruction must be
used to ensure sequential ordering of
loads with stores.
The MPC7450 guarantees that any load followed by any store is
performed in order (with respect to each
other). The reverse, however, is not guaranteed. An eieio instruction
must be inserted between a store
followed by a load to ensure sequential ordering between that store
and that load. Also note that setting
HID0[SPD] does not prevent loads from bypassing stores.

I've one processor, why should I use tlbsync instruction in page table
updates? And why should I use eieio instruction in this context?

Thanks a lot.
0
lc
4/28/2008 3:58:31 PM
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